参数资料
型号: KMPC8313EZQAFFB
厂商: Freescale Semiconductor
文件页数: 89/99页
文件大小: 0K
描述: IC MPU POWERQUICC II 516-PBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
封装/外壳: 516-BBGA 裸露焊盘
供应商设备封装: 516-PBGAPGE(27x27)
包装: 托盘
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
9
This figure shows the undershoot and overshoot voltages at the interfaces of the MPC8313E.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths.
Note:
1. GVDD, NVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction.
2. Some GPIO pins may operate from a 2.5-V supply when configured for other functions.
3. Min temperature is specified with TA; Max temperature is specified with TJ.
4. All Power rails must be connected and power applied to the MPC8313 even if the IP interfaces are not used.
5. All I/O pins should be interfaced with peripherals operating at same voltage level.
6. This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering” and not necessarily the voltage at the
AVDD pin, which may be reduced from VDD by the filter.
Table 3. Output Drive Capability
Driver Type
Output Impedance (
)
Supply Voltage
Local bus interface utilities signals
42
NVDD = 3.3 V
PCI signals
25
DDR signal
18
GVDD = 2.5 V
Table 2. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended Value1
Unit
Current
Requirement
VSS
VSS – 0.3 V
VSS – 0.7 V
Not to Exceed 10%
G/L/NVDD + 20%
G/L/NVDD
G/L/NVDD + 5%
of tinterface
1
1. Note that tinterface refers to the clock period associated with the bus clock
VIH
VIL
Note:
interface.
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