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参数资料
| 型号： | KS8695PX-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 16/40页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695PX |
| 标准包装： | 1 |
| 相关产品： | KS8695PXA3-ND - IC ARM9 W/MMU 5PORT 289-PBGA KS8695PX-ND - IC SWITCH 10/100 1PORT 289PBGA |
| 其它名称： | 576-1004 |
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M9999-091605
23
September 2005
KS8695PX
Micrel
Signal Descriptions by Group
Clock and Reset Pins
Pin
Name
I/O Type(1)
Description
E1
XCLK1/
I
External Clock In. This signal is used as the source clock for the transmit clock of the
CPUCLK
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
E2
XCLK2
I
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
M15
URTSN/
O/I
Normal Mode: UART request to send. Active low output.
CPUCLKSEL
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
A17
RESETN
I
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695PX. When in the reset state, all the output pins are tri-
stated
and all open drain signals are oating.
U17
WRSTO
O
Watchdog timer reset output. This signal is asserted for at least 200ms if
RESETN is asserted or when the internal watchdog timer expires.
T17
EROEN/
O/I
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
WRSTPLS
asserted, this signal controls the output enable port of the specied device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
Name
I/O Type(1)
Description
G14
TCK
I
JTAG test clock.
G15
TMS
I
JTAG test mode select.
F14
TDI
I
JTAG test data in.
F15
TDO
O
JTAG test data out.
F16
TRSTN
I
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
Name
I/O Type(1)
Description
G1
WANTXP
O
WAN PHY transmit signal + (differential).
G2
WANTXM
O
WAN PHY transmit signal – (differential).
G3
WANRXP
I
WAN PHY receive signal + (differential).
G4
WANRXM
I
WAN PHY receive signal – (differential).
G5
WANFXSD
I
WAN ber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb ber mode. See Application Note 10.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KS8695X | 功能描述:IC SWITCH 10/100 5PORT 208PQFP RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| KS8695X_11 | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:Integrated Multi-Port High-Performance Gateway Solution Rev. 1.03 |
| KS8695X-EVAL | 功能描述:BOARD EVAL EXPERIMENT KS8695X RoHS:否 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 主要目的:电源管理，电池充电器 嵌入式:否 已用 IC / 零件:MAX8903A 主要属性:1 芯锂离子电池 次要属性:状态 LED 已供物品:板 |
| KS86C4004 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-pr |
| KS86C4104 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-pr |
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