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参数资料
| 型号： | KS8695PX-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 3/40页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695PX |
| 标准包装： | 1 |
| 相关产品： | KS8695PXA3-ND - IC ARM9 W/MMU 5PORT 289-PBGA KS8695PX-ND - IC SWITCH 10/100 1PORT 289PBGA |
| 其它名称： | 576-1004 |
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September 2005
11
M9999-091605
KS8695PX
Micrel
Pin Number
Pin Name
Type(1)
Pin Function
P15
RCSN0
O
ROM/SRAM/FLASH Chip Select. Active Low.
R15
RCSN1
O
ROM/SRAM/FLASH Chip Select. Active Low.
B4
REQ1N
I
PCI Bus Request 1. Active Low. Input for Host Bridge Mode and Guest Bridge
Mode.
B3
NC
—
No Connect
B2
NC
—
No Connect
A17
RESETN
I
KS8695PX Chip Reset. Active Low.
T5
SDCASN
O
SDRAM Column Address Strobe. Active Low.
P5
SDCSN0
O
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
R4
SDCSN1
O
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
T7
SDICLK
I
SDRAM Clock In.
U7
SDOCLK
O
System/SDRAM Clock Out.
U6
SDQM0
O
SDRAM Data Input/Output Mask.
T6
SDQM1
O
SDRAM Data Input/Output Mask.
R6
SDQM2
O
SDRAM Data Input/Output Mask.
P6
SDQM3
O
SDRAM Data Input/Output Mask.
R5
SDRASN
O
SDRAM Row Address Strobe. Active Low.
U5
SDWEN
O
SDRAM Write Enable. Active Low.
A10
SERRN
O
PCI System Error Signal. Active Low.
D11
STOPN
I/O
PCI Stop Signal. Active Low.
G14
TCK
I
JTAG Test Clock.
F14
TDI
I
JTAG Test Data In.
F15
TDO
O
JTAG Test Data Out.
M4
TEST1
I
PHY Test Pin (factory reserved test signal).
F4
TEST2
I
PHY Test Pin (factory reserved test signal).
F17
TESTEN
I
Chip Test Enable (factory reserved test signal). Must be connected to GND for
normal operation
G15
TMS
I
JTAG Test Mode Select
C10
TRDYN
I/O
PCI Target Ready Signal. Active Low.
F16
TRSTN
I
JTAG Test Reset. Active Low.
M14
UCTSN/
I
UART Data Set Ready. Active Low. BIST Enable (factory reserved test signal).
BISTEN
L15
UDCDN/
I
UART Data Carrier Detect. Scan Enable (factory reserved test signal).
SCANEN
M16
UDSRN
I
UART Data Set Ready. Active Low.
N15
UDTRN/
O/I
UART Data Terminal Ready. Active Low. Debug Enable (factory reserved test .
DBGENN
signal)
L14
URIN/TSTRST
I
UART Ring Indicator/Chip Test Reset (factory reserved test signal).
M15
URTSN/
O/I
UART Request to Send/CPU Clock Select.
CPUCLKSEL
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
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