参数资料
型号: KS8993
厂商: Micrel Inc
文件页数: 14/35页
文件大小: 0K
描述: IC SWITCH 10/100 3PORT 128PQFP
标准包装: 66
系列: *
类型: *
应用: *
安装类型: 表面贴装
封装/外壳: 128-BFQFP
供应商设备封装: 128-PQFP(14x20)
配用: 576-1011-ND - BOARD EVAL EXPERIMENT FOR KS8993
May 2005
21
KS8993
Micrel
MII Interface Operation
The MII (Media Independent Interface) operates in either a forward or reverse mode. In the forward mode, the KS8993 MII acts
like a MAC and in the reverse mode, it acts like a PHY device. This interface is specified by the IEEE 802.3 committee and
provides a common interface between physical layer and MAC layer devices. There are two distinct groups, one being for
transmission and the other for receiving. The table below describes the signals used in this interface in forward and reverse
modes.
This interface is a nibble wide data interface and therefore runs at 1/4 the network bit rate (not encoded). Additional signals
on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has
indicators that convey when the data is valid and without physical layer errors.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII interface for the KS8993 for reverse operation and MTXER is not
represented for forward mode. Normally this would indicate a receive / transmit error coming from the physical layer /MAC
device, but is not appropriate for this configuration. If the connecting device has a MRXER pin, this should be tied low on the
other device for reverse or if it has a MTXER pin in the forward mode it should also be tied low on the other device.
Reverse MII Mode Connection
Forward MII Mode Connection
External MAC
KS8993 Signal
Description
External PHY
KS8993 Signal
MTXEN
Transmit enable
MTXEN
MRXDV
MTXER
Transmit error
MTXER
Not used
MTXD3
MTXD[3]
Transmit data bit 3
MTXD3
MRXD[3]
MTXD2
MTXD[2]
Transmit data bit 2
MTXD2
MRXD[2]
MTXD1
MTXD[1]
Transmit data bit 1
MTXD1
MRXD[1]
MTXD0
MTXD[0]
Transmit data bit 0
MTXD0
MRXD[0]
MTXC
MTXCLK
Transmit clock
MTXC
MTXCLK
MCOL
Collision detection
MCOL
MCOLIN
MCRS
Carrier sense
MCRS
MRXDV
Receive data valid
MRXDV
MTXEN
MRXER
Not used
Receive error
MRXER
MTXER
MRXD3
MRXD[3]
Receive data bit 3
MRXD3
MTXD[3]
MRXD2
MRXD[2]
Receive data bit 2
MRXD2
MTXD[2]
MRXD1
MRXD[1]
Receive data bit 1
MRXD1
MTXD[1]
MRXD0
MRXD[0]
Receive data bit 0
MRXD0
MTXD[0]
MRXC
MRXCLK
Receive clock
MRXC
MRXCLK
Table 2. MII Interconnect
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