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参数资料
| 型号： | KSZ8001SL TR |
| 厂商： | Micrel Inc |
| 文件页数： | 43/46页 |
| 文件大小： | 0K |
| 描述： | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 类型： | 收发器 |
| 规程： | MII，RMII，SMII |
| 电源电压： | 1.8V, 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 配用： | 576-1620-ND - BOARD EVALUATION FOR KSZ8001L |
| 其它名称： | KSZ8001SLTR KSZ8001SLTR-ND |
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Micrel
KSZ8001
June 2009
Revision 1.04
6
Pin Description
Pin Number
Pin Name
Type
(Note 1)
Pin Function
1
MDIO
I/O
MII Management (MIIM) Interface: Data I/O
This pin requires an external 4.7K pull-up resistor.
2
MDC
I
MII Management (MIIM) Interface: Clock Input
This pin is synchronous to the MDIO data line.
3
RXD3/
PHYAD1
Ipd/O
MII Mode: Receive Data Output[3]
2 /
Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[1]
during reset. See “Strapping Options” section for details.
4
RXD2/
PHYAD2
Ipd/O
MII Mode: MII Receive Data Output[2]
2 /
Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[2]
during reset. See “Strapping Options” section for details.
5
RXD1/
RXD[1]/
PHYAD3
Ipd/O
MII Mode: Receive Data Output[1]
2 /
RMII Mode: Receive Data Output[1]
3 /
Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[3]
during reset. See “Strapping Options” section for details.
6
RXD0/
RXD[0]/
RX
PHYAD4
Ipd/O
MII Mode: Receive Data Output[0]
2 /
RMII Mode: Receive Data Output[0]
3 /
SMII Mode: Receive Data and Control
4 /
Configuration Mode: The pull-up/pull-down value is latched as PHYADDR[4]
during reset. See “Strapping Options” section for details.
7
VDDIO
Pwr
3.3V digital VDD
8
GND
Gnd
Ground
9
RXDV/
CRSDV/
PCS_LPBK
Ipd/O
MII Mode: Receive Data Valid Output /
RMII Mode: Carrier Sense/Receive Data Valid /
Configuration Mode: The pull-up/pull-down value is latched as pcs_lpbk
during reset. See “Strapping Options” section for details.
10
RXC/
SMII_SELE
CT
Ipd/O
MII Receive Clock Output
Operating at:
25 MHz = 100 Mbps
2.5 MHz = 10 Mbps
Configuration Mode: The pull-up/pull-down value is latched as SMII during
reset. See “Strapping Options” section for details.
11
RXER/
RX_ER/
ISO
Ipd/O
MII Mode: Receive Error Output /
RMII Mode: Receive Error /
Configuration Mode: The pull-up/pull-down value is latched as ISOLATE
during reset. See “Strapping Options” section for details.
12
GND
Gnd
Ground
13
VDDC
Pwr
1.8V digital core VDD
VDD output
:
KSZ8001L / KSZ8001SL
VDD input
:
KSZ8001S
(See “Circuit Design Reference for Power Supply” section for details)
14
TXER
Ipd
MII Transmit Error Input
15
TXC/
REFCLK/
CLOCK
I/O
MII Mode: MII Transmit Clock Output /
RMII Mode: 50 MHz Reference Clock Input /
SMII Mode: 125 MHz Synchronization Clock Input
16
TXEN
Ipd
MII Transmit Enable Input
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