参数资料
型号: KSZ8031RNL-EVAL
厂商: Micrel Inc
文件页数: 5/43页
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8031RNL
标准包装: 1
主要目的: 接口,以太网 PHY
嵌入式:
已用 IC / 零件: KSZ8031RNL
已供物品:
相关产品: 576-3843-6-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3843-1-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3788-ND - TXRX PHY 10/100 3.3V 24-QFN
576-3843-2-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3741-5-ND - TXRX PHY 100BASE TX 3.3V 24QFN
其它名称: 576-3862
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
13
M9999-082710-1.0
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RXP and
RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the
incoming signal and the KSZ8021/31RNL decodes a data frame. The receive clock is kept active during idle periods in
between data reception.
Scrambler/De-Scrambler (100Base-TX Only)
The scrambler is used to spread the power spectrum of the transmitted signal to reduce EMI and baseline wander, and
the de-scrambler is needed to recover the scrambled signal.
PLL Clock Synthesizer
The KSZ8021/31RNL in RMII – 25MHz Clock Mode generates all internal clocks and all external clocks for system timing
from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8021/31RNL in RMII – 50MHz Clock Mode,
these clocks are generated from an external 50MHz oscillator or system clock.
Auto-Negotiation
The KSZ8021/31RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
Priority 1: 100Base-TX, full-duplex
Priority 2: 100Base-TX, half-duplex
Priority 3: 10Base-T, full-duplex
Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8021/31RNL link partner is forced to bypass auto-negotiation, then the
KSZ8021/31RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8021/31RNL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (ANEN_SPEED, pin 23) or software (register 0h, bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. Afterwards, auto-negotiation can be enabled or
disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is
set by register 0h, bit [8].
The auto-negotiation link up process is shown in Figure 1.
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