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参数资料
| 型号： | KSZ8721BL TR |
| 厂商： | Micrel Inc |
| 文件页数： | 2/35页 |
| 文件大小： | 0K |
| 描述： | IC TXRX PHY 10/100 3.3V 48LQFP |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | MII，RMII |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC 576-1626-ND - BOARD EVALUATION FOR KSZ8721BL |
| 其它名称： | 576-1028-6 |
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Micrel, Inc.
KS8721BL/SL
June 2009
10
M9999-062509-1.3
Strapping Options
(1)
Pin Number
Pin Name
Type
(2)
Pin Function
6, 5,
4, 3
PHYAD[4:1]/
RXD[0:3]
Ipd/O
25
PHYAD0/
INT#
Ipu/O
PHY Address latched at power-up/reset. The default PHY address is 00001.
9
(3)
PCS_LPBK/
RXDV
Ipd/O
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
11
(3)
ISO/RXER
Ipd/O
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
21
(3)
RMII/COL
Ipd/O
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
22
(3)
RMII_BTB
CRS
Ipd/O
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
PU = Enable.
27
SPD100/
No FEF/
Ipu/O
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) =
100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
28
DUPLEX/
LED2
Ipu/O
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) =
Full-duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex
support in register 4h.
29
NWAYEN/
LED3
Ipu/O
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/reset.
PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
30
PD#
Ipu
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
Notes:
1.
Strap-in is latched during power-up or reset.
2.
Ipu = Input with internal pull-up.
Ipd/O = Input with internal pull-down during reset; output pin otherwise.
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and oat information.
3.
Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset.
It is recommended that an external pull-down via 1k resistor be used in these applications to augment the 8721’s internal pull-down.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8721BMC-EVAL | 功能描述:以太网开发工具 KSZ8721BMC Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8721BT | 功能描述:以太网 IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-TQFP (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8721BTA4 | 功能描述:TXRX 10/100 3.3V 48-TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KSZ8721BT-EVAL | 功能描述:以太网开发工具 KSZ8721BT Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8721BTR | 制造商:Micrel 功能描述:Physical Layer Transceiver 1Ch 100Mbps |
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