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参数资料
| 型号： | KSZ8721BL TR |
| 厂商： | Micrel Inc |
| 文件页数： | 6/35页 |
| 文件大小： | 0K |
| 描述： | IC TXRX PHY 10/100 3.3V 48LQFP |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | MII，RMII |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1627-ND - BOARD EVALUATION FOR KSZ8721BMC 576-1626-ND - BOARD EVALUATION FOR KSZ8721BL |
| 其它名称： | 576-1028-6 |
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Micrel, Inc.
KS8721BL/SL
June 2009
14
M9999-062509-1.3
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0],
and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide
REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock
distribution device. Each PHY device must have an input corresponding to this clock but may use a single clock input
for multiple PHYs implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is,
in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are
detected, the carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV
remains continuously asserted from the rst recovered di-bit of the frame through the nal recovered di-bit and is
negated prior to the rst REF_CLK that follows the nal di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is
asynchronous relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes
place (see “Denition of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0]
transfers two bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions),
a predetermined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle
when CRS_DV is de-asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-
of-band signaling (to be dened). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the
MAC/repeater. Upon assertion of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes
place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN
is asserted synchronously with the rst nibble of the preamble and remains asserted while all transmitted di-bits are
presented to the RMII. TX_EN is negated prior to the rst REF_CLK following the nal di-bit of a frame. TX_EN
transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is de-asserted. Values of
TXD[1:0] other than “00” when TX_EN is de-asserted are reserved for out-of-band signaling (to be dened). Values
other than “00” on TXD[1:0] while TX_EN is de-asserted are ignored by the PHY.
Collision Detection
Since the denition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably
re-generates the COL signal of the MII by ANDing TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers
as a self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL
signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was
functioning. Since the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
RX_ER
The PHY provides RX_ER as an output according to the rules specied in IEEE 802.3u [2] (see Clause 24, Figure 24-
11– Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a
coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-
layer) is detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously
with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8721BMC-EVAL | 功能描述:以太网开发工具 KSZ8721BMC Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8721BT | 功能描述:以太网 IC 10/100 Base-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-TQFP (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8721BTA4 | 功能描述:TXRX 10/100 3.3V 48-TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KSZ8721BT-EVAL | 功能描述:以太网开发工具 KSZ8721BT Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8721BTR | 制造商:Micrel 功能描述:Physical Layer Transceiver 1Ch 100Mbps |
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