参数资料
| 型号： | KSZ8863MLLI |
| 厂商： | Micrel Inc |
| 文件页数： | 85/106页 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 48-LQFP |
| 标准包装： | 250 |
| 控制器类型： | 以太网开关控制器 |
| 接口： | MII |
| 电源电压： | 1.8V，2.5V，3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 配用： | 576-3867-ND - BOARD EVALUATION FOR KSZ8863MLL |
| 其它名称： | 576-3751 |
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PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 79
13.1
DC Characteristics:
PIC16C72/CR72-04 (Commercial, Industrial, Extended)
PIC16C72/CR72-10 (Commercial, Industrial, Extended)
PIC16C72/CR72-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40C
≤ TA ≤ +125C for extended,
-40C
≤ TA ≤ +85C for industrial and
0C
≤ TA ≤ +70C for commercial
Param
No.
Characteristic
Sym
PIC16C72
PIC16CR72
Units
Conditions
Min
Typ
Max
Min
Typ
Max
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
6.0
5.5
4.0
4.5
-
5.5
5.5
V
XT, RC and LP osc
HS osc
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-
on Reset Signal
VPOR
-
VSS
-
VSS
-
V
See section on Power-
on Reset for details
D004*
VDD rise rate to ensure
internal Power-on
Reset Signal
SVDD
0.05
-
0.05
-
V/ms
See section on Power-
on Reset for details
D005
Brown-out Reset Volt-
age
Bvdd
3.7
4.0
4.3
3.7
4.0
4.3
V
BODEN bit in congura-
tion word enabled
3.7
4.0
4.4
3.7
4.0
4.4
V
Extended Only
D010
Supply Current
(Note 2,5)
IDD
-
2.7
5.0
-
2.7
5.0
mA
XT, RC osc
FOSC = 4 MHz,
VDD = 5.5V (Note 4)
D013
-
10
20
-
10
20
mA
HS osc
FOSC = 20 MHz,
VDD = 5.5V
D015
Brown-out Reset
Current (Note 6)
Ibor
-
350
425
-
350
425
A
BOR enabled,
VDD = 5.0V
D020
Power-down Current
(Note 3,5)
IPD
-
10.5
42
-
10.5
42
A
VDD = 4.0V, WDT
enabled, -40
°C to +85°C
D021
-
1.5
16
-
1.5
16
A
VDD = 4.0V, WDT dis-
abled, -0
°C to +70°C
D021A
-
1.5
19
-
1.5
19
A
VDD = 4.0V, WDT dis-
abled, -40
°C to +85°C
D021B
-
2.5
19
-
2.5
19
A
VDD = 4.0V, WDT dis-
abled, -40
°C to +125°C
D023
Brown-out Reset
Current (Note 6)
Ibor
-
350
425
-
350
425
A
BOR enabled VDD =
5.0V
*
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1:
This is the limit to which VDD can be lowered without losing RAM data.
Note 2:
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specied.
Note 3:
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
Note 4:
For RC osc conguration, current through Rext is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Note 5:
Timer1 oscillator (when enabled) adds approximately 20
A to the specication. This value is from characterization and
is for design guidance only. This is not tested.
Note 6:
The
current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
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