参数资料
型号: KSZ8893FQL-FX
厂商: Micrel Inc
文件页数: 2/117页
文件大小: 0K
描述: IC SWITCH ETH 3PORT 128-PQFP
标准包装: 66
控制器类型: 以太网开关控制器
接口: MII,RMII,SNI
电源电压: 3.1 V ~ 3.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-BFQFP
供应商设备封装: 128-PQFP(14x20)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-1603-ND - EVAL KIT EXPERIMENTAL KSZ8893MQL
其它名称: 576-3273
Micrel, Inc.
KSZ8893FQL
October 2007
10
M9999-101607-1.3
List of Figures
Figure 1. TS-1000 OAM Frame Format ........................................................................................................................... 23
Figure 2. Typical TS-1000 Media Converter Application ................................................................................................. 24
Figure 3. KSZ8893FQL MC Loop Back Paths ................................................................................................................. 25
Figure 4. Typical Straight Cable Connection ................................................................................................................... 31
Figure 5. Typical Crossover Cable Connection ............................................................................................................... 31
Figure 6. Auto-Negotiation and Parallel Operation. ......................................................................................................... 32
Figure 7. Destination Address Lookup Flow Chart, Stage 1............................................................................................ 35
Figure 8. Destination Address Resolution Flow Chart, Stage 2....................................................................................... 36
Figure 9. 802.1p Priority Field Format.............................................................................................................................. 46
Figure 10. KSZ8893FQL EEPROM Configuration Timing Diagram. ............................................................................... 48
Figure 11. SPI Write Data Cycle. ..................................................................................................................................... 50
Figure 12. SPI Read Data Cycle. ..................................................................................................................................... 50
Figure 13. SPI Multiple Write. .......................................................................................................................................... 51
Figure 14. SPI Multiple Read. .......................................................................................................................................... 51
Figure 15. Far-End Loopback Path. ................................................................................................................................. 52
Figure 16. Near-end (Remote) Loopback Path................................................................................................................ 53
Figure 17. EEPROM Interface Input Timing Diagram.................................................................................................... 106
Figure 18. EEPROM Interface Output Timing Diagram ................................................................................................. 106
Figure 19. SNI Timing – Data Received from SNI ......................................................................................................... 107
Figure 20. SNI Timing – Data Input-to-SNI .................................................................................................................... 107
Figure 21. MII Timing – Data Received from MII ........................................................................................................... 108
Figure 22. MII Timing – Data Input-to-MII ...................................................................................................................... 108
Figure 23. RMII Timing – Data Received from RMII ...................................................................................................... 109
Figure 24. RMII Timing – Data Input-to-RMII................................................................................................................. 109
Figure 25. SPI Input Timing ........................................................................................................................................... 110
Figure 26. SPI Output Timing......................................................................................................................................... 111
Figure 27. Auto-Negotiation Timing ............................................................................................................................... 112
Figure 28. Reset Timing................................................................................................................................................. 113
Figure 29. Recommended Reset Circuit........................................................................................................................ 114
Figure 30. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output................................................ 114
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