参数资料
型号: KSZ9021GNI
厂商: Micrel Inc
文件页数: 6/53页
文件大小: 0K
描述: TXRX GIG ETH GMII/MII 64-QFN
标准包装: 348
类型: 收发器
驱动器/接收器数: 8/8
规程: 千兆位以太网
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-QFN(8x8)
包装: 托盘
配用: 576-3873-ND - BOARD EVALUATION FOR KSZ9021GN
其它名称: 576-3789
Micrel, Inc.
KSZ9021GN
September 2010
14
M9999-091010-1.1
Strapping Options
Pin Number
Pin Name
Type
(1)
Pin Function
48
17
19
PHYAD2
PHYAD1
PHYAD0
I/O
The PHY Address, PHYAD[2:0], is latched at power-up / reset and is configurable to
any value from 1 to 7. Each PHY address bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY Address bits [4:3] are always set to ‘00’.
39
41
43
44
MODE3
MODE2
MODE1
MODE0
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as
follows:
MODE[3:0]
Mode
0000
Reserved – not used
0001
GMII / MII Mode
0010
Reserved – not used
0011
Reserved – not used
0100
NAND Tree Mode
0101
Reserved – not used
0110
Reserved – not used
0111
Chip Power Down Mode
1000
Reserved – not used
1001
Reserved – not used
1010
Reserved – not used
1011
Reserved – not used
1100
Reserved – not used
1101
Reserved – not used
1110
Reserved – not used
1111
Reserved – not used
45
CLK125_EN
I/O
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 55 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
55
LED_MODE
I/O
LED_MODE is latched at power-up / reset and is defined as follows:
Pull-up = Single LED Mode
Pull-down = Tri-color Dual LED Mode
Note:
1.
I/O = Bi-directional.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched to the incorrect
configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure
the PHY is configured to the correct pin strap-in mode.
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