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| 型号： | KXPC8240LVV200E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 49/52页 |
| 文件大小： | 0K |
| 描述： | IC MPU INTEGRATED 250MHZ 352TBGA |
| 标准包装： | 2 |
| 系列： | MPC82xx |
| 处理器类型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 电压： | 2.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 352-LBGA |
| 供应商设备封装： | 352-TBGA（35x35） |
| 包装： | 托盘 |
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6
MPC8240 Integrated Processor Hardware Specifications
Electrical and Thermal Characteristics
1.4.1.2
Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8240.
Table 2. Recommended Operating Conditions 1
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
VDD
2.5
± 5%
V
4, 6
Supply voltage for PCI and standard bus standards
OVDD
3.3
± 0.3
V
6
Supply voltages for memory bus drivers
GVDD
3.3
± 5%
V
8
PLL supply voltage—CPU core logic
AVDD
2.5
± 5%
V
4, 6
PLL supply voltage—peripheral logic
AVDD22.5 ± 5%
V
4, 7
DLL supply voltage
LAVDD
2.5
± 5%
V
4, 7
PCI reference
LVDD
5.0
± 5%
V
9, 10
3.3
± 0.3
V
9, 10
Input voltage
LVDD input-tolerant signals
Vin
0 to 3.6 or 5.75
V
2, 3
All other inputs
0 to 3.6
V
5
Die-junction temperature
Tj
0 to 105
°C
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. These signals are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3- or 5.0-V DC power
supply.
3. LVDD input tolerant signals: PCI interface, PIC control, and OSC_IN signals.
Cautions:
5. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2/LAVDD) by more than 2.5 V at all
times, including during power-on reset.
6. OVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. VDD/AVDD/AVDD2/LAVDD must not exceed OVDD by more than 0.6 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. GVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. LVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 5.4 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LVDD must not exceed OVDD by more than 3.6 V at any time, including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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