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参数资料
| 型号： | KXTF9-4100 |
| 厂商： | Kionix Inc |
| 文件页数： | 12/49页 |
| 文件大小： | 0K |
| 描述： | IC ACCELEROMETER TRI-AXIS 10-LGA |
| 应用说明： | Sensor Handling, Mounting, Soldering KXTF9 Getting Started |
| 标准包装： | 1 |
| 系列： | KXTF9 |
| 轴： | X，Y，Z |
| 加速范围： | ±2g，4g，8g |
| 灵敏度： | 64计数/g，32计数/g，16计数/g（8位，1024计数/g，512计数/g，256计数/g（12位） |
| 电源电压： | * |
| 输出类型： | 数字 - I²C |
| 带宽： | 400Hz |
| 接口： | I²C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFLGA |
| 供应商设备封装： | 10-LGA（3x3） |
| 其它名称： | 1191-1001-6 |
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PART NUMBER:
± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
KXTF9-4100
Rev. 6
Jun-2011
KXTF9 Digital Interface
The Kionix KXTF9 digital accelerometer has the ability to communicate on the I 2 C digital serial interface bus.
This flexibility allows for easy system integration by eliminating analog-to-digital converter requirements and by
providing direct communication with system micro-controllers.
The serial interface terms and descriptions as indicated in Table 6 below will be observed throughout this
document.
Term
Transmitter
Receiver
Master
Slave
Description
The device that transmits data to the bus.
The device that receives data from the bus.
The device that initiates a transfer, generates clock signals, and terminates a transfer.
The device addressed by the Master.
Table 6. Serial Interface Terminologies
I 2 C Serial Interface
As previously mentioned, the KXTF9 has the ability to communicate on an I 2 C bus. I 2 C is primarily used for
synchronous serial communication between a Master device and one or more Slave devices. The Master,
typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The
KXTF9 always operates as a Slave device during standard Master-Slave I 2 C operation.
I 2 C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a
serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a
wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is
transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per
transfer is unlimited. The I 2 C bus is considered free when both lines are high.
I 2 C Operation
Transactions on the I 2 C bus begin after the Master transmits a start condition (S), which is defined as a high-
to-low transition on the data line while the SCL line is held high. The bus is considered busy after this
condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the
seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be
receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, eac h
device on the bus compares the seven MSBs with its internally stored address. If they match, the device
considers itself addressed by the Master. The Slave Address associated with the KXTF9 is 0001111.
36 Thornwood Dr. – Ithaca, NY 14850
tel: 607-257-1080 – fax:607-257-1146
www.kionix.com - info@kionix.com
? 2010 Kionix – All Rights Reserved
425-2397-1106241613
Page 12 of 49
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