参数资料
型号: L5985TR
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: 2 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO8
封装: 3 X 3 MM, 1.08 MM HEIGHT, LEAD FREE, VFQFPN-8
文件页数: 11/37页
文件大小: 856K
代理商: L5985TR
L5985
Application information
Doc ID 13006 Rev 5
19/37
5.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2
π * ESR * C
OUT < 1/BW), the type III
compensation network is needed. Multi layer ceramic capacitors (MLCC) have very low ESR
(< 1 m
Ω), with very high frequency zero, so type III network is adopted to compensate the
loop.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 16
Equation 17
Figure 10.
Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 GLC(f))
and the open loop gain (GLOOP(f) = GPW0 GLC(f) GTYPEIII(f)) are drawn.
f
Z1
1
2
π C
3
R
1
R
3
+
()
------------------------------------------------
=
f
Z2
1
2
π R
4
C
4
------------------------------
=
,
f
P0
0
=
f
P1
1
2
π R
3
C
3
------------------------------
=
f
P2
1
2
π R
4
C
4
C
5
C
4
C
5
+
--------------------
--------------------------------------------
=
,,
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