
PIN DESCRIPTION (continued)
Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)
Power down sequencing, POR, other voltage pins
PIN #
PIN NAME
DESCRIPTION
PIN
TYPE
I\O
MAPPED?
TRI-STATE
@SLEEP/@POR
13
VRECT
Output of the synchronous rectifier supplying power to
the retract circuitry. Filtered by an internal 400pF
capacitor. Normally not externally connected. However,
if retract command is to be used, a small signal silicon
diode must be connected between this pin and Vcc
(Cathode to VRECT) to supply the additional current
which may be required to brake the VCM.
AO
No
28
BRK_DLY
An external parallel RC network from this point to
ground sets the Brake dELAY:T = 0.45 RC.
Typical values are R = 4M
, C=0.1F (0.16sec,
delay).
ANo
No
30
VPDOWN
Voltage tripler reservoir capacitor. This is used for
the brake operation when power is removed from
the chip. No DC load allowed. 1
F minimum, 10F
prefered.
ANo
No
61
C1HIGH
Positive terminal of charge pump capacitor.
10nF (typ) for Tripler operation;
330nF (typ0 or Doubler operation
ANo
No
62
C1LOW
Negative terminal of charge pump capacitor.
10nF (typ) for Tripler operation;
330nF (typ) or Doubler operation
ANo
No
64
C2HIGH
Positive terminal of charge pump capacitor for
Tripler operation. 330nF (typ).
Connected tp VHRTRIP for Doubler operation.
ANo
No
2
C2LOW
Negative terminal of charge pump capacitor for
Tripler operation. 330nF (typ).
Not connected for Doubler operation.
ANo
No
52
POR_DLY
An external capacitor from this pin to ground sets
the duration of POR after power has been re-
established. T (por) = 32 X C (por)
where: C (por) is in pF and T is expresssed in
s.
ANo
No
5
POR
Power On Reset. This open drain output goes low
when the voltage at either UV1 or UV2 goes below
1.25V.
DO
Yes
No
50
UV1
Under voltage detector 1. This defines the
VOLTAGE GOOD threshold by comparing the
voltage on this pin to the internal 1.25V reference.
An external resistor divider network and capacitor
filter provides the selection of threshold and supply
noise rejection. There is an internal pull-up (2
A
max). Hysteresis is 20mV.
AI
Yes
No
51
SPN_DSBL_
DLY
Spindle Disable Delay . A capacitor connected
between this pin and Vcc programs the delay
between POR and the disabling of the Spindle
section..
Delay = 80 xC (C in pF; Delay in
s)
AI
Yes
No
4
VHTRIP
High tripler/Doubler output. 330nF (typ). 11V max.
AO
No
3
VLTRIP
Low tripler/Doubler output. 330nF (typ). for stability.
AO
No
L6260
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