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参数资料
| 型号： | L6713ATR |
| 厂商： | Holtek Semiconductor Inc. |
| 英文描述： | 2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs |
| 中文描述： | 2 / 3为英特尔VR10，VR11和AMD的嵌入式驱动器相控制器6位CPU |
| 文件页数： | 49/64页 |
| 文件大小： | 515K |
| 代理商： | L6713ATR |
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L6713A
System control loop compensation
53/64
Removing the dependence from the Error Amplifier gain, so assuming this gain high
enough, and with further simplifications, the control loop gain results:
The system Control Loop gain (See Figure 26) is designed in order to obtain a high DC gain
to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the
desired crossover frequency
ωT. Neglecting the effect of ZF(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance
ωLC) and the zero (ωESR) is fixed by ESR and the Droop resistance.
Figure 26. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).
To obtain the desired shape an RF-CF series network is considered for the ZF(s)
implementation. A zero at
ωF=1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero
ωF in correspondence with the L-
C resonance assures a simple -20dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing
ωF = ωLC and imposing the cross-
over frequency
ωT as desired obtaining (always considering that ωT might be not higher than
1/10th of the switching frequency FSW):
Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a
capacitor between COMP pin and FB pin (it does not change the system bandwidth:
G
LOOP
s
()
4
5
---
V
IN
V
OSC
----------------------
Z
F
s
()
R
FB
---------------
R
O
R
DROOP
+
R
O
R
L
N
-------
+
--------------------------------------------
1s
C
O
R
DROOP
//R
O
ESR
+
()
+
s
2
C
O
L
N
-----
s
L
N
R
O
----------------------
C
O
ESR
C
O
R
L
N
-------
++
1
+
+
-------------------------------------------------------------------------------------------------------------------------------------------------------------
–
=
VREF
FB
COMP
VSEN
FBG
RF
CF
RFB
DROOP
PWM
L / N
ESR
CO
RO
d VOUT
VOUT
ZF(s)
ZFB(s)
I DR
OOP
dB
ω
ZF(s)
GLOOP(s)
K
ω
LC = ωF
ω
ESR
ω
T
RF[dB]
CP
R
F
R
FB
V
OSC
V
IN
-------------------------------------
5
4
---
ω
T
L
NR
DROOP
ESR
+
()
-----------------------------------------------------------
=
C
F
C
O
L
N
----
R
F
------------------------
=
C
P
1
2
π R
F
NF
SW
-----------------------------------------------------------
=
相关PDF资料 |
PDF描述 |
|---|---|
| L6713A | 2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs |
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| L8C201JC15 | x9 Asynchronous FIFO |
| L8C202JI10 | x9 Asynchronous FIFO |
| L8C202JI12 | x9 Asynchronous FIFO |
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