参数资料
型号: L6717
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: DUAL SWITCHING CONTROLLER, 575 kHz SWITCHING FREQ-MAX, QCC48
封装: 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFPN-48
文件页数: 30/56页
文件大小: 1081K
代理商: L6717
Output voltage positioning
L6717
36/56
Doc ID 17326 Rev 1
Figure 10.
Current reading
The current read through the CSxP / CSxN pairs is converted into a current IINFOx propor-
tional to the current delivered by each phase and the information about the average current
IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The
error between the read current IINFOx and the reference IAVG is then converted into a voltage
that with a proper gain is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
7.3
CORE section - defining load-line
L6717 introduces a dependence of the output voltage on the load current recovering part of
the drop due to the output capacitor ESR in the load transient. Introducing a dependence of
the output voltage on the load current, a static error, proportional to the output current,
causes the output voltage to vary according to the sensed current.
Figure 10 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor(s) is read through the R - C filter across CSxP and CSxN pins. RG
programs a trans-conductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current, with proper gain defined by the DRP_ADJ com-
mand (kDRP), is then sourced by the FB pin (kDRPIDROOP). RFB gives the final gain to pro-
gram the desired load-line slope (Figure 9).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system so avoiding over
and/or under shoot of the output voltage as a consequence of a load transient. See
Section 7.2. The output characteristic vs. load current is then given by:
Where RLL is the resulting load-line resistance implemented by the CORE Section. kDRP
value is determined by the Power Manager I2C and its default value is 1/4.
RFB resistor can be then designed according to the RLL specifications and DRP_ADJ setting
as follow:
See Section 6.2 for details about DRP_ADJ command.
Lx
CSxP
CSxN
DCRx
R
C
RG
I
PHASEx
Inductor DCR Current Sense
ICSxN=IINFOx
V
OUT
V
CORE
VID
R
FB
k
DRP
I
DROOP
VID
k
DRP
R
FB
DCR
R
G
------------- I
OUT
VID
R
LL
I
OUT
==
=
R
FB
R
LL
k
DRP
-------------
R
G
DCR
-------------
=
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