参数资料
型号: L6726ATR
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: 1.5 A SWITCHING CONTROLLER, 297 kHz SWITCHING FREQ-MAX, PDSO8
封装: SOP-8
文件页数: 10/35页
文件大小: 986K
代理商: L6726ATR
Application details
L6726A
18/35
Doc ID 12754 Rev 4
8.3
Soft-start time calculation
To calculate SS time (tSS), the following approximated equation can be used (CP<<CF):
The previous equation refers only to VOUT ramp up time. The time elapsed from the end of
OC setting phase or COMP set free to the beginning of VOUT ramp up (see Figure 6) can be
approximately estimated as follow:
Once calculated tSS, also the current delivered by the converter during SS to charge the
output capacitor bank can be estimated:
8.4
Layout guidelines
L6726A provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 10) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 10.
Power connections (heavy lines)
The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper number of vias when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
t
SS
C
F
V
OUT
V
IN
--------------
ΔV
OSC
I
SS
--------------------------------------------------
=
t
delay
C
F
0.8V
I
SS
------------------------
=
I
startup
C
OUT
V
OUT
t
SS
----------------------------------
=
L
CIN
VIN
UGATE
PHASE
LGATE
GND
LOAD
L6726A
COUT
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