参数资料
型号: L6728A
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, PDSO10
封装: 3 X 3 MM, VFDFPN-10
文件页数: 6/32页
文件大小: 1223K
代理商: L6728A
Obsolete
Product(s)
- Obsolete
Product(s)
L6728A
Application details
9
Application details
9.1
Compensation network
The control loop showed in Figure 5 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with VIN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT. This function has a double pole at frequency FLC depending on the L-C output
filter and a zero at FESR depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔV
OSC.
Figure 5.
PWM control loop
The compensation network closes the loop joining VOUT and EA output with transfer
function ideally equal to -ZF/ZFB.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F0dB) can be fixed choosing the right RF/RFB ratio, however, for
stability, it should not exceed FSW/2π. To achieve a good phase margin, the control loop gain
has to cross 0 dB axis with -20 dB/decade slope.
As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
L
R
C
OUT
ESR
R
F
C
F
C
P
R
FB
C
S
OSC
V
IN
ΔV
OSC
+
_
V
OUT
V
REF
ZF
Z
FB
PWM
COMPARATOR
ERROR
AMPLIFIER
R
S
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