参数资料
型号: L6728A
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, PDSO10
封装: 3 X 3 MM, VFDFPN-10
文件页数: 8/32页
文件大小: 1223K
代理商: L6728A
Obsolete
Product(s)
- Obsolete
Product(s)
L6728A
Application details
b)
Place FZ1 below FLC (typically 0.5*FLC):
c)
Place FP1 at FESR:
d)
Place FZ2 at FLC and FP2 at half of the switching frequency:
e)
Check that compensation network gain is lower than open loop EA gain before
F0dB;
f)
Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
9.2
Layout guidelines
L6728A provides control functions and high current integrated drivers to implement high-
current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 7) must be a part of a power plane and anyway realized by wide and thick copper
traces: loop must be anyway minimized. The critical components, i.e. the power MOSFETs,
must be close one to the other. The use of multi-layer printed circuit board is recommended.
The input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
same high-current trace on more than one PCB layer will reduce the parasitic resistance
associated to that connection.
Connect output bulk capacitors (COUT) as near as possible to the load, minimizing parasitic
inductance and resistance associated to the copper trace, also adding extra decoupling
capacitors along the way to the load when this results in being far from the bulk capacitors
bank.
C
F
1
π R
F
LC
-----------------------------
=
C
P
C
F
2
π R
F
C
F
ESR
1
----------------------------------------------------------
=
R
S
R
FB
F
SW
2F
LC
------------------
1
---------------------------
=
C
S
1
π R
S
F
SW
-------------------------------
=
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