参数资料
型号: L6918DTR
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PDSO28
封装: SO-28
文件页数: 32/35页
文件大小: 431K
代理商: L6918DTR
L6918 L6918A
6/35
16
ISEN2
Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the current intervention for each
phase at 140% as follow:
Where 35
A is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
17
OSC/INH
FAULT
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according
to the equation:
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stops operation and enters the inhibit
state; all mosfets are turned OFF.
The pin is forced high when an over voltage is detected. This condition is latched; to recover it
is necessary turn off and on VCC.
18
SYNC_OUT
Output synchronization signal. A60
° phase shift signal exits when the device works as a Slave
while no signal exits when the device works as an adjustable.
19
SYNC / ADJ
Slave or Adjustable operation.
Connecting this pin to GND the device becomes an adjustable two-phase controller using an
external reference for its regulation. No soft start is implemented in this condition, so it must be
performed with external circuitry. The device switches using its internal oscillator according to
the frequency set by ROSC.
Leaving this pin floating, the device works as a Slave two-phase controller. It uses the
reference sourced from the master device and an internal PLL locks the synchronization signal
sourced from the master device.
20
SLAVE_OK
Open-drainoutput used for start-up and to manage protections as shown in the timing diagram. Internally
pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF capacitor vs. SGND.
21
SYNC_IN
Synchronization input signal locked during the slave operation. Connect to the master SYNC_OUT pin.
22
VPROG_IN
Reference voltage input used for voltage regulation.
This pin must be connected together with the other’s slave (if present) to the VPROG_OUT pin
of the master device.
Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed).
If the device works as an Adjustable (SYNC/ADJ to GND), this is the reference used for the regulation.
23
PGOOD
This pin is an open collector output and is pulled low if the output voltage is not within the
above specified thresholds. It must be connected with the master’s PGOO D pin.
If not used may be left floating.
L6918 (SLAVE) PIN FUNCTION (continued)
N.
Name
Description
I
OCPx
35
AR
g
R
sense
--------------------------
=
f
S
300KHz
14.82 10
6
R
OSC K
()
-----------------------------
+
=
f
S
300KHz
12.91 10
7
R
OSC K
()
-----------------------------
+
=
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