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参数资料
| 型号： | L7C174KMB25 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | SRAM |
| 英文描述： | 8K X 8 CACHE TAG SRAM, 22 ns, CQCC32 |
| 封装： | CERAMIC, LCC-32 |
| 文件页数： | 6/8页 |
| 文件大小： | 60K |
| 代理商： | L7C174KMB25 |
DEVICES INCORPORATED
L7C174
8K x 8 Cache-Tag Static RAM
Special Architecture Static RAMs
03/26/1999–LDS.174-M
6
1. Maximum Ratings indicate stress specifi-
cations only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating con-
ditions for extended periods may affect re-
liability of the tested device.
2. The products described by this specifica-
tion include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive elec-
trical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2.0 V. The device can withstand in-
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. Duration of the output short circuit
should not exceed 30 seconds.
5. A series of normalized curves is available
to supply the designer with typical DC and
AC parametric information for Logic Devices
Static RAMs. These curves may be used to
determine device characteristics at various
temperatures and voltage levels.
6. Tested with all address and data inputs
changing at the maximum cycle rate. The
device is continuously enabled for writing,
i.e., CE
≤ VIL, WE ≤ VIL. Input pulse levels
are 0 to 3.0 V.
7. Tested with outputs open and all address
and data inputs changing at the maximum
read cycle rate. The device is continuously
disabled, i.e., CE
≥ VIH.
8. Tested with outputs open and all address
and data inputs stable. The device is con-
tinuously disabled, i.e., CE = VCC. Input
levels are within 0.2 V of VCC or GND.
9. Data retention operation requires that
VCC
never drop below 2.0 V. CE must be
≥ VCC – 0.2 V. All other inputs must meet
VIN
≥ VCC – 0.2 V or VIN ≤ 0.2 V to ensure
full powerdown. For low power version (if
applicable), this requirement applies only to
CE and WE; there are no restrictions on data
and address.
10. These parameters are guaranteed but
not 100% tested.
11. Test conditions assume input transition
times of less than 3 ns, reference levels of
1.5 V, output loading for specified IOL and
NOTES
IOH
plus 30 pF (Figs. 1a and 1c), and input
pulse levels of 0 to 3.0 V (Fig. 2).
12. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
tAVEW
is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
ments of all parts. Responses from the inter-
nal circuitry are specified from the point of
view of the device. Access time, for ex-
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
13. WE is high for the read cycle.
14. The chip is continuously selected (CE
low).
15. All address lines are valid prior-to or
coincident-with the CE transition to active.
16. The internal write cycle of the memory
is defined by the overlap of CE active and
WE low. All three signals must be active to
initiate a write. Any signal can terminate a
write by going inactive. The address, data,
and control input setup and hold times
should be referenced to the signal that be-
comes active last or becomes inactive first.
17. If WE goes low before or concurrent
with the latter of CE going active, the output
remains in a high impedance state.
18. If CE goes inactive before or concurrent
with WE going high, the output remains in
a high impedance state.
19. Powerup from ICC2 to ICC1 occurs as a
result of any of the following conditions:
a. Falling edge of CE.
b. Falling edge of WE (CE active).
c. Transition on any address line (CE
active).
d. Transition on any data line (CE, and WE
active).
The device automatically powers down
from ICC1 to ICC2 after tPD has elapsed from
any of the prior conditions. This means that
power dissipation is dependent on only
cycle rate, and is not on Chip Select pulse
width.
20. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
21. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 1b. This parameter is sampled and
not 100% tested.
22. All address timings are referenced from
the last valid address line to the first transi-
tioning address line.
23. CE or WE must be inactive during ad-
dress transitions.
24. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the VCC and ground planes di-
rectly up to the contactor fingers. A 0.01 F
high frequency capacitor is also required
between VCC and ground. To avoid signal
reflections, proper terminations must be
used.
FIGURE 1a.
+5 V
OUTPUT
R1 480
30 pF
R2
255
INCLUDING
JIG AND
SCOPE
<3 ns
GND
+3.0 V
90%
10%
90%
10%
<3 ns
FIGURE 2.
FIGURE 1c.
+5 V
L7C174
MATCH
PIN
30 pF
INCLUDING
JIG AND
SCOPE
R1 200
FIGURE 1b.
+5 V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R1 480
R2
255
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