Multiplexer MUX1 is used for test purposes. In normal operation the 32kHz clock signal is passed to sig-
nal SBCLK. In test mode however (pin TEST=high) the main clock can be supplied to the peripheral
components and the RC oscillator can be stopped by setting bit TEST of oscillator control register
OSCR.
Multiplexer MUX2 is used to select main clock or standby clock for TIMER1 and watchdog under control
of signal STOP which is active in STOP mode of the CPU.
The RC oscillator is designed to minimize frequency offset caused by temperature, supply voltage,
manufacturing tolerances. Nevertheless the deviation from 32kHz might be larger than required and tun-
ing will become necessary. For that purpose the RC oscillator frequency can be measured and adjusted
under control of the CPU as described in the following (see also fig. 7).
The device is in normal operation mode (pin TEST=low). The standby oscillator is controlled by oscillator
control register OSCR. Setting bit TEST of OSCR will connect the TIMER1 input with signal GATE via
MUX3. The timer now has to be initialized and programmed to input gated mode. In this mode it will
count clock pulses (fMAINCLK
±12) as long as its input is high. If bit COUNT of OSCR is set now, the block
COUNT LOGIC generates one pulse at signal GATE with the length of exactly one period of the RC os-
cillator clock signal. Therefore the timer will count main/oscillator pulses for one period of the standby
clock. At the falling edge of signal GATE bit READY of OSCR is set indicating the end of the measure-
ment. Now the timer can be read by the CPU to determine the actual frequency of the standby oscillator.
Bits TEST, COUNT, READY can be cleared now. As long as COUNT is set, READY can not be cleared
by software.
Timer resolution at fMAINCLK = 8MHz is 12
125ns = 1.5s.
Measurement of a clock period of TGATE = 1/32kHz = 31.3
s therefore shows a resolution of about 5%.
The RC oscillator has a nominal frequency of 32kHz and can be adjusted with frequency control bits
FC2, 1, 0. Adjustment is performed in steps of 4kHz (i. e. 12.5%) from 16kHz to 44kHz as shown in the
following table.
FC2
FC1
FC0
fRCOSC/kHz
00
0
44
00
1
40
01
0
36
01
1
32
10
0
28
10
1
24
11
0
20
11
1
16
Register OSCR is cleared at system reset. Therefore the highest frequency of RC oscillator is selected.
Bits 5 and 6 are not implemented. They are read as zero.
MICROCONTROLLER SECTION (continued)
SBCLK
COUNT
GATE
READY
TGATE
=1/fSBCLK
TGATE
Figure 7. Signals of RC oscillator count logic.
L9942
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