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参数资料
| 型号： | L9952GXPTR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO36 |
| 封装： | LEAD FREE, SSO-36 |
| 文件页数： | 17/68页 |
| 文件大小： | 859K |
| 代理商： | L9952GXPTR |
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Description
L9952GXP
Doc ID 13518 Rev 5
2.20.2
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety
function is implemented to avoid an activation of the output stages by a wrong
communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
2.20.3
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the global error flag (fault condition).
The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer
the content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
2.20.4
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to 1MHz.
2.20.5
Data registers
The device has 3 Control registers and 2 Status registers. The first two bits (D22+D23) at
the DI-Input are used to select one of the Control registers. All bits are first shifted into an
input shift register. After the rising edge of CSN the contents of the input shift register will be
written to the selected Control register only if a frame of exact 24 bits is detected. If the
Control register 1 is selected for data transfer, the Status register 1 will be transferred to the
DO during the current communication frame. For the selection of Control register 0 or
Control register 2, the Status register 0 is transferred to DO.
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