参数资料
型号: LAMXO2280E-3TN144E
厂商: Lattice Semiconductor Corporation
文件页数: 5/77页
文件大小: 0K
描述: IC FPGA AUTO 2.28KLUTS 144-TQFP
标准包装: 60
系列: LA-MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 5.1ns
电压电源 - 内部: 1.14 V ~ 1.26 V
宏单元数: 1140
输入/输出数: 113
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
2-10
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Table 2-5. PLL Signal Descriptions
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory
The LA-MachXO1200 and LA-MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR
consists of a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Congurations
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from
CLKINTFB port
RST
I
“1” to reset the input clock divider
CLKOS
O
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output clock to clock tree (No phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
LOCK
O
“1” indicates PLL LOCK to CLKI
CLKINTFB
O
Internal feedback source, CLKOP divider output before CLOCKTREE
DDAMODE
I
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
DDAIZR
I
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
DDAILAG
I
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
DDAIDEL[2:0]
I
Dynamic Delay Input
Memory Mode
Congurations
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
True Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
Pseudo Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
FIFO
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
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