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参数资料
| 型号： | LB1825 |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 2 A, PDIP28 |
| 封装： | HEAT SINK, DIP-28 |
| 文件页数： | 2/9页 |
| 文件大小： | 139K |
| 代理商： | LB1825 |
Allowable Operating Ranges at Ta = 25°C
Electrical Characteristics at Ta = 25°C, VCC = 24 V
No. 4845-2/9
LB1825
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VCC
10 to 28
V
Parameter
Symbol
Conditions
min
typ
max
Unit
ICC1
Braking stopped mode
35
47
mA
Current drain
ICC2
FGOUT1 stopped mode
35
47
mA
ICC3
External clock, braking stopped mode
28
40
mA
Upper transistor (1)
VO (sat)1
IO = 1.0 A
1.0
1.6
V
Upper transistor (2)
VO (sat)2
IO = 1.5 A
1.25
2.1
V
Lower transistor (1)
VO (sat)1
IO = 1.0 A
0.6
1.0
V
Lower transistor (2)
VO (sat)2
IO = 1.5 A
0.9
1.6
V
Output leakage current
IO LEAK
100
A
[Fixed voltage block]
Output voltage
VREG
IREG = 20 mA
6.3
7.0
7.8
V
Output current
IREG
20
mA
Load variation
V
REG
IREG = 0 to 20 mA
0.25
V
Temperature coefficient
αV
REG
Design target value
–2.0
mV/°C
[Hall input block]
Input bias current
IB (HA)
1
4
A
Common-mode input range
1.5
VCC – 1.8
V
Input sensitivity
DVH
20
mV
Input offset voltage
VIOH
20
mV
[Drive block]
Dead zone width
VDZ
50
200
mV
Output idling voltage
VID
6
mV
Forward gain
GDF+
0.4
0.5
0.6
Reverse gain
GDF–
–0.6
–0.5
–0.4
Accelerate command voltage
VSTA
6.0
6.3
V
Decelerate command voltage
VSTO
0.8
1.5
V
Forward limiter voltage
VL+
Rf = 1.8
0.45
0.53
0.61
V
Reverse limiter voltage
VL–
Rf = 1.8
0.45
0.53
0.61
V
[Phase comparator block]
Output high level voltage
VPDH
No external load
VREG – 0.4
V
Output low level voltage
VPDL
No external load
0.4
V
Output source current
IPD+
0.4
mA
Output sink current
IPD–
2.5
mA
[Error amplifier block]
Input bias current
IB (ER)
1
A
Input offset voltage
VIO (ER)
–10
+10
mV
Output high level voltage
VERH
No external load
5.5
V
Output low level voltage
VERL
No external load
1.0
V
[Lock detector block]
Output saturation voltage
VLD (sat)
ILD = 10 mA
0.4
V
[FG amplifier block]
Input bias current
IB (FG)
1
A
Input offset voltage
VIO (FG)
–10
+10
mV
Output high level voltage
VFGH
No external load
5.0
V
Output low level voltage
VFGL
No external load
2.0
V
[FG Schmitt block]
Input operating level
VIS
FGOUT1 generation signal
160
mVp-p
Input hysteresis (high
→ low)
VSHL
External clock, braking stopped mode
0
mV
Input hysteresis (low
→ high)
VSLH
External clock, braking stopped mode
36
mV
Hysteresis
VFGS
18
36
60
mV
Output saturation voltage
VFG2 (sat) IFG2 = 10 mA
0.4
V
Continued on next page.
Output
saturation
voltage
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