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参数资料
| 型号： | LB1875 |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 0.03 A, PDSO36 |
| 封装： | HSOP-36 |
| 文件页数： | 2/17页 |
| 文件大小： | 335K |
| 代理商： | LB1875 |
LB1875
No. 6002-10/17
Oscillator frequency (MHz)
C1 (
μF)
C2 (pF)
C3 (pF)
R1 (
)
2 to 3
0.1
10
100
330k
3 to 7
0.1
None
47
330k
7 to 9
0.1
None
22
330k
9 to 10
0.1
None
12
330k
4. Reference clock
Since the clock input of the PLL circuit (CLK
IN) and the internal divisor output (CLKOUT) are separate, various applications are
possible.
(1) Using the internal divider circuit
Basically, CLK
IN and CLKOUT are shorted. If a division ratio other than the built-in ratio is required, an external divider circuit can be
inserted between these two pins.
[1] Using a quartz oscillator
An oscillator using a quartz crystal and C, R components can be configured as shown below.
The circuit configuration and values are for reference only. The quartz crystal characteristics as well as the possibility of floating
capacitance and noise due to layout factors must be taken into consideration when designing an actual application.
[Precautions for wiring layout design]
Since the quartz oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the
circuit board. Wiring should be kept as short as possible and traces should be kept narrow.
[2] External clock input (equivalent to quartz oscillator, several MHz)
When using an external signal source instead of a quartz oscillator, a resistor of about 13 k
Ω should be inserted in series at the XI
input. The XO pin should be left open.
Signal input level
Low: 0 to 0.8 V
High: 2.5 to 5 V
(2) When not using the internal divider circuit
When using an external signal source to supply a signal equivalent to the FG frequency (several kHz), the signal is input via the
CLK
IN pin. When not using a quartz oscillator, the XI pin should be left open or connected to the VREG pin (XO is open).
5. Hall input signal
The Hall input requires a signal with an amplitude of at least the hysteresis width (24 mV max.). Taking possible noise influences
into consideration, an amplitude of at least 100 mV is desirable. If noise at the Hall input is a problem, a noise-canceling capacitor
(about 0.001 to 0.1
μF) should be connected across the Hall input pins .
Since the same-phase input range is 0 to V
CC–2V, a Hall element can be connected in series if 12V is applied at the VCC pin.
6. FG input signal
The FG input is designed mainly for input from a Hall element and has the same specifications as the Hall input. If the input is to be
used for an FG pattern or other very low-level signal, an external amplifier must be used to amplify the signal first.
When there is noise at the FG input, locking may be impaired and jitter may increase. If PWM switching noise or other noise is found
to be present, countermeasures such as making the Hall element power supply more stable or connecting a capacitor across the input
will be necessary.
(Reference values)
C1, R1 : For stable oscillation
C2 : For overtone oscillation prevention
C3 : For crystal coupling
XI
XO
VREG
C1
C2
C3
R1
A11349
Ω
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