参数资料
型号: LC4256B-10FN256AI
厂商: Lattice Semiconductor Corporation
文件页数: 98/99页
文件大小: 0K
描述: IC PLD 256MC 128IO 10NS 256FPBGA
标准包装: 90
系列: ispMACH® 4000B
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 10.0ns
电压电源 - 内部: 2.3 V ~ 2.7 V
逻辑元件/逻辑块数目: 16
宏单元数: 256
输入/输出数: 160
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 256-BGA
供应商设备封装: 256-FPBGA(17x17)
包装: 托盘
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V (3.3V) Lead-Free Extended Temperature Devices
Pin/Ball
Device
LC4032V
LC4064V
LC4128V
LC4256V
Part Number
LC4032V-75TN48E
LC4032V-75TN44E
LC4064V-75TN100E
LC4064V-75TN48E
LC4064V-75TN44E
LC4128V-75TN144E
LC4128V-75TN128E
LC4128V-75TN100E
LC4256V-75TN176E
LC4256V-75TN144E
LC4256V-75TN100E
Macrocells
32
32
64
64
64
128
128
128
256
256
256
Voltage
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
t PD
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
Package
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Lead-free TQFP
Count
48
44
100
48
44
144
128
100
176
144
100
I/O
32
30
64
32
30
96
92
64
128
96
64
Grade
E
E
E
E
E
E
E
E
E
E
E
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH
4000V/B/C/Z family:
Revision History
Date
July 2003
October 2003
December 2003
Version
17z
18z
19z
Change Summary
Previous Lattice releases.
Changed device status for LC4064ZC and LC4128ZC to production release and updated/added
AC and DC parameters as well as ordering part numbers for LC4064ZC and LC4128ZC devices.
Improved leakage current specifications for ispMACH 4000Z. For ispMACH 4000V/B/C IIL, IIH
condition now includes 0V and 3.6V end points (0 ? VIN ? 3.6V).
Added 132-ball chip scale BGA power supply and NC connections.
Added 132-ball chip scale BGA logic signal connections for LC4064ZC, LC4128ZC and
LC4256ZC devices.
Added lead-free package designators.
Hot socketing characteristics footnote 1. has been enhanced; Insensitive to sequence of VCC or
VCCO. However, assumes monotonic rise/fall rates for Vcc and Vcco, provided (VIN - VCCO) ?
3.6V.
Improved LC4064ZC t S to 2.5ns, t ST to 2.7ns and f MAX (Ext.) to 175MHz, LC4128ZC t CO to 3.5ns
and f MAX (Ext.) to 161MHz (version v.2.1).
Improved associated internal timing numbers and timing adders (version v.2.1).
Added ispMACH 4000V/B/C/Z ORP Reference Tables.
Enhanced ORP information in device pinout tables consistent with the ORP Combinations for I/O
Blocks tables (table 6, 7, 8 and 9 in page 9-11).
Corrected GLB/MC/Pad information in the 256-fpBGA pinouts for the LC4256V/B/C 160-I/O ver-
sion.
Added the ispMACH 4000 Family Speed Grade Offering table.
Added the ispMACH 4128ZC Industrial and Automotive Device OPNs
Added the ispMACH 4032ZC and 4064ZC Industrial and Automotive Device OPNs
98
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