参数资料
型号: LC4384V-75TN176C
厂商: Lattice Semiconductor Corporation
文件页数: 29/99页
文件大小: 0K
描述: IC CPLD 384MACROCELLS 176TQFP
标准包装: 40
系列: ispMACH® 4000V
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 24
宏单元数: 384
输入/输出数: 128
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 176-LQFP
供应商设备封装: 176-TQFP(24x24)
包装: 托盘
其它名称: 220-1716
LC4384V-75TN176C-ND
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters
Over Recommended Operating Conditions
-5
-75
-10
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
In/Out Delays
t IN
t GOE
t GCLK_IN
t BUF
t EN
t DIS
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
0.95
4.04
1.83
1.00
0.96
0.96
1.50
6.04
2.28
1.50
0.96
0.96
2.00
7.04
3.28
1.50
0.96
0.96
ns
ns
ns
ns
ns
ns
Routing/GLB Delays
t ROUTE
t MCELL
t INREG
t FBK
t PDb
t PDi
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
1.51
1.05
0.56
0.00
1.54
0.94
2.26
1.45
0.96
0.00
2.24
1.24
3.26
1.95
1.46
0.00
3.24
1.74
ns
ns
ns
ns
ns
ns
Register/Latch Delays
t S
t S_PT
t ST
t ST_PT
t H
t HT
t SIR
t SIR_PT
t HIR
t HIR_PT
t COi
t CES
t CEH
t SL
t SL_PT
t HL
t GOi
t PDLi
t SRi
t SRR
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-Register Setup Time (Product Term Clock)
D-Register Hold Time
T-Register Hold Time
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to Output/Feedback MUX
Delay
Asynchronous Reset or Set Recovery Time
1.32
1.32
1.52
1.32
1.68
1.68
1.52
1.45
0.68
0.68
2.25
1.88
1.32
1.32
1.17
0.28
1.67
0.52
0.33
0.25
1.57
1.32
1.77
1.32
2.93
2.93
1.57
1.45
1.18
1.18
2.25
1.88
1.57
1.32
1.17
0.28
1.67
0.67
0.33
0.25
1.57
1.32
1.77
1.32
3.93
3.93
1.57
1.45
1.18
1.18
2.25
1.88
1.57
1.32
1.17
0.28
1.67
1.17
0.33
0.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Delays
t BCLK
t PTCLK
t BSR
t PTSR
GLB PT Clock Delay
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
1.12
0.87
1.83
2.51
1.12
0.87
1.83
3.41
0.62
0.87
1.83
3.41
ns
ns
ns
ns
29
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