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| 型号： | LC4512B-10FN256I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 10 ns, PBGA256 |
| 封装： | LEAD FREE, FPBGA-256 |
| 文件页数： | 5/99页 |
| 文件大小： | 441K |
| 代理商： | LC4512B-10FN256I |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
13
Figure 10. Global OE Generation for ispMACH 4032
Zero Power/Low Power and Power Management
The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E
2 low power cell and non sense-amplier design approach (full CMOS logic
approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low
standby power without needing any “turbo bits” or other power management schemes associated with a traditional
sense-amplier approach.
The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verication. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.
I/O Quick Conguration
To facilitate the most efcient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for conguration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows
this by offering the user the ability to quickly congure the physical nature of the I/O cells. This quick conguration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's ispVM
System programming software can either perform the quick conguration through the PC parallel port, or can gen-
erate the ATE or test vectors necessary for a third-party test system.
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Global
Fuses
GOE (3:0)
to I/O cells
Internal Global OE
PT Bus
(2 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
相关PDF资料 |
PDF描述 |
|---|---|
| LC4384C-5FN256I | |
| LC4512B-35FN256C | |
| LC4256B-5FN256BC | |
| LC4256C-5FN256BC | |
| LC4256B-10FN256BI | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC4512B-10FN256I1 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4512B-10FT256I | 功能描述:CPLD - 复杂可编程逻辑器件 ispJTAG 2.5V 10nsIND 512MC 208 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4512B-10FTN256I | 功能描述:CPLD - 复杂可编程逻辑器件 ispJTAG 2.5V 10nsIND 512MC 208 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4512B-10T176I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC4512B-10TN176I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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