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参数资料
型号： LC51024MV-75F484C
厂商： Lattice Semiconductor Corporation
文件页数： 7/99页
文件大小： 0K
描述： IC XPLD 1024MC 7.5NS 484FPBGA
标准包装： 60
系列： ispXPLD® 5000MV
可编程类型： 系统内可编程
最大延迟时间 tpd(1)： 7.5ns
电压电源 - 内部： 3 V ~ 3.6 V
逻辑元件/逻辑块数目： 32
宏单元数： 1024
输入/输出数： 317
工作温度： 0°C ~ 90°C
安装类型： 表面贴装
封装/外壳： 484-BBGA
供应商设备封装： 484-FPBGA（23x23）
包装： 托盘
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
11
Pseudo Dual-Port SRAM Mode
In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Register
Input
Source
Write Address, Write
Data, Write Enable,
and Write Chip Select
Clock
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
Clock Enable
WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
Read Data and Read
Address
Clock
RCLK or one of the global clocks (CLK0 - CLK3). The selected signal can be
inverted if desired.
Clock Enable
RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
‘
68 Inputs
From
Routing
16,384 bit
Pseudo
Dual
Port
SRAM
Array
Write Address
(WAD[0:8-13])
Write Clk Enable (WCEN)
Write Clock (WCLK)
Read Address
(RAD[0:8-13])
Write Enable (WE)
Write Chip Sel (WCS[0,1])
Reset (RST)
Read Clk Enable (RCEN)
Read Clock (RCLK)
Write Data
(WD[0:0,1,3,7,15,31])
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(RD[0:0-15])
SELECT
DEVICES
DISCONTINUED
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LC51024MV-75F484I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC51024MV-75F672C 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC51024MV-75F672I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC51024MV-75FN208C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC51024MV-75FN208I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
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