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参数资料
| 型号： | LC5512MB-75F484I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 9.5 ns, PBGA484 |
| 封装： | FPBGA-484 |
| 文件页数： | 13/95页 |
| 文件大小： | 923K |
| 代理商： | LC5512MB-75F484I |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
20
Programmable Slew Rate
The slew rate of outputs is carefully controlled. When outputs are configured as LVCMOS the devices support two
slew rates. This allows system noise and performance to be balanced in a design.
Programmable Bus-Maintenance
All general-purpose inputs have programmable bus maintenance circuitry. These are intended to maintain a valid
logic level into a device when driving devices go into the tri-state mode. Four options are available for users: pull-
up, pull-down, bus-keeper, or nothing.
Expanded In-System Programmability (ispXP)
The ispXPLD 5000MX family utilizes a combination of EEPROM non-volatile cells and SRAM technology to deliver
a logic solution that provides “instant-on” at power-up, a convenient single chip solution, and the capability for infi-
nite reconfiguration. A non-volatile array distributed within the device stores the device configuration. At power-up
this information is transferred in a massively parallel fashion into SRAM bits that control the operation of the device.
Figure 18 shows the different ports and modes that are used in the configuration and programming of the ispXPLD
5000MX devices.
Figure 18. ispXP Block Diagram
IEEE 1532 ISP
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispXPLD 5000MX devices provide
in-system programmability through their Boundary Scan Test Access Port. This capability has been implemented in
a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the
communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined inter-
face.
The IEEE1532 programming interface allows programming of either the non-volatile array or reconfiguration of the
SRAM bits.
The ispXPLD 5000MX devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispXPLD 5000MX devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispXPLD 5000MX devices during the testing
of a circuit board.
SRAM
Memory Space
E2CMOS
Memory Space
sysCONFIG Peripheral Port
sysCONFIG
ISP 1149.1 TAP Port
Power-up
Refresh
Programming
in seconds
Download in
microseconds
Configuration
in milliseconds
Port
Mode
Memory Space
ISP
1532
BACKGND
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| LC5512MB-75F672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-75F672I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-75FN208C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-75FN208I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-75FN256C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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