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参数资料
| 型号： | LC7153 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 10/11页 |
| 文件大小： | 167K |
| 代理商： | LC7153 |
LC7153, 7153M
No.4160–8/11
Table 4. Unlock detector thresholds
0
L
U1
L
U
e
s
a
h
p
B
D
L
,
A
D
L
d
l
o
h
s
e
r
h
t
r
o
r
e
)
s
(
s
d
l
o
h
s
e
r
h
t
r
o
r
e
s
a
h
p
e
l
p
m
a
x
E
f
N
I
X
z
H
M
4
=f
N
I
X
z
H
M
2
.
7
=f
N
I
X
z
H
M
8
=f
N
I
X
z
H
M
4
2
.
0
1
=f
N
I
X
z
H
M
8
.
2
1
=
00
0
00000
10
f
/
4
±
N
I
X
0
.
1
±5
5
.
0
±0
5
.
0
±9
3
.
0
±1
3
.
0
±
01
f
/
6
1
±
N
I
X
0
.
4
±2
2
.
2
±0
0
.
2
±6
5
.
1
±0
2
.
1
±
11
f
/
4
6
±
N
I
X
0
.
6
1
±8
8
.
8
±0
0
.
8
±5
2
.
6
±0
0
.
5
±
Bits UE0 and UE1 determine the unlock extension, or de-
lay, before the unlock detector outputs, LDA and LDB, can
change state. The extension for different reference frequen-
cies is shown in table 5. However, if a phase-error thresh-
old of zero is set using UL0 and UL1, no output extension
occurs.
Table 5. LDA, LDB output extension
0
E
U1
E
U
t
u
p
t
u
o
B
D
L
,
A
D
L
n
o
i
s
n
e
t
x
e
)
s
m
(
s
n
o
i
s
n
e
t
x
e
t
u
p
t
u
o
e
l
p
m
a
x
E
f f
e
r
z
H
k
1
=f f
e
r
z
H
k
5
=f f
e
r
z
H
k
5
.
2
1
=
00
f
/
4
f
e
r
)
p
y
t
(
0
.
48
.
02
3
.
0
10
f
/
8
f
e
r
0
.
86
.
14
6
.
0
01
f
/
2
3
f
e
r
0
.
2
3)
p
y
t
(
4
.
66
5
.
2
11
f
/
4
6
f
e
r
0
.
4
68
.
2
1)
p
y
t
(
2
1
.
5
Bit DZ is the dead-zone selection bit. It selects the phase-
insensitive bandwidth, or dead zone, of the phase compara-
tor. When DZ=1, DZB mode is selected, and when DZ=0,
DZA mode. DZB mode has larger dead zone than DZA
mode.
Bits T0, T1 and T2 are test bits. They should be set to 0 for
normal operation.
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