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参数资料
| 型号： | LC7185-8750 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PDIP30 |
| 封装： | SDIP-30 |
| 文件页数： | 8/12页 |
| 文件大小： | 152K |
| 代理商： | LC7185-8750 |
Pin Description
Pin Name
Pin No.
Type
Description
TX
30
.
Transmit/receive select
TX = ‘‘0’’...Transmit, TX = ‘‘1’’...Receive
HOLD
26
.
Hold mode select
HOLD = ‘‘0’’...Hold mode select
=‘‘1’’...Normal mode select
INIT
25
.
Reset line
INIT = ‘‘0’’...Reset
TEST
22
.
Test point (input)
Tieto ground or leave floating
VDD
24
.
Power supply (+)
Normal mode: 5.0 to 8.0 V
Hold mode:
^ 3.2 V
VSS221
.
Channel display LED driver ground
PIN
23
.
Programmable divider input
150 mVrms min
Hold mode: Programmable divider is disabled.
XIN
XOUT
20
19
.
Crystal oscillator
Frequency: 10.24 MHz
Hold mode: Oscillator is disabled.
PD
27
.
Charge pump output from the phase comparator. If the frequency of fV
(the signal obtained by dividing the PIN input by N) is higher than that of
fR (the reference signal), or if the phase of fV leads that of fR, positive
pulses are output on this pin. If the frequency is lower or the phase lags,
negative pulses are output on this pin. If they match, the pin goes to high
impedance.
.
fV > fR OR leading: Positive Pulses
.
fV < fR OR leading: Negative Pulses
.
fV = fR and phase muched: High impedance
Hold mode: High impedance
VSS128
.
PLL circuit and controller ground
NC
29
.
No-connection
UL
18
.
Unlock detected output
Fixed to low level when unlocked, when changing channels, in PA mode,
or in hold mode.
Open: Locked
BEEP
17
.
Beep-tone control output
During station memory operation
During I/O on emergency channel
When changing channels
—
During reset
During hold mode recovery
Fixed to low level in hold mode
Transistor: Off (50 ms cycle)
→ Open
SA to SG
1 to 7
.
Segment drivers for the display
(Common anode/7 segments)
D1
D2
8
9
.
Digit output (150 Hz) for the display
(common anode/7 segments)
Hold mode: Transistor goes off.
Continued on next page.
LC7185-8750
No. 3356-5/12
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