参数资料
型号: LC72121
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP22
封装: DIP-22
文件页数: 6/23页
文件大小: 377K
代理商: LC72121
Structure of the Programmable Divider
Sample Programmable Divider Divisor Calculations
For FM with a step size of 50 kHz (DVS = 1, SNS = *: FMIN selected)
FM RF = 90.0 MHz (IF +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 0)
100.7 MHz (FM VCO)
÷ 25 kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) 2014 → 07DE (hexadecimal)
*: Don’t care
No. 5815-14/23
LC72121, 72121M, 72121V
DVS
SNS
Input pin
Set divisor
Actual divisor
Input frequency range
A
1
*
FMIN
272 to 65535
Twice the set value
10 to 160 MHz
B
0
1
AMIN
272 to 65535
The set value
2 to 40 MHz
C
0
AMIN
4 to 4095
The set value
0.5 to 10 MHz
For SW with a step size of 5 kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected)
SW RF = 21.75 MHz (IF +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 1)
22.2 MHz (SW VCO)
÷ 5 kHz (fref) = 4440 → 1158 (hexadecimal)
For MW with a step size of 9 kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected)
MW RF = 1008 kHz (IF +450 kHz)
WM VCO = 1458 kHz
PLL fref =9 kHz (R0 = 1, R1 = 0, R2 = 0, R3 = 1)
1458 (MW VCO)
÷ 9 kHz (fref) = 162 → 0A2 (hexadecimal)
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参数描述
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