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参数资料
| 型号： | LC72121M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 20/23页 |
| 文件大小： | 377K |
| 代理商： | LC72121M |
No. 5815-6/23
LC72121, 72121M, 72121V
Continued from preceding page.
Pin
Pin No.
Type
Function
Equivalent circuit
name
LC72121
Chip enable
This pin must be set high to enable serial data input (DI) or serial
data output (DO).
CE
3
LC72121M
LC72121V
Input data
Input for serial data transferred from the controller
DI
4
Clock
Clock used for data synchronization for serial data input (DI) and
serial data output (DO).
CL
5
Output data
Output for serial data transmitted to the controller. The content of the
data transmitted is determined by DOC0 through DOC2.
DO
6
Power supply
LC72121 power supply (VDD 2.7 to 3.6 V)
The power on reset circuit operates when power is first applied.
——
VDD
17
18
Ground
Ground for the crystal oscillator circuit
——
VSSX
2
Ground
Ground for the low-pass filter MOS transistor
——
VSSa
21
22
Ground
Ground for the LC72121 digital systems other than those that use
VSSa or VSSX.
——
VSSd
14
15
I/O port
Shared function I/O ports
The pin function is determined by IOC1 and IOC2 in the serial data.
When the data value 0: Input port
When the data value 1: Output port
When specified to function as an input port:
The input pin state is reported to the controller through the DO pin.
When the input state is low: The data will be 0:
When the input state is high: The data will be 1:
When specified to function as an output port:
The output state is determined by IO1 and IO2 in the serial data.
When the data value is 0: The output state will be the open circuit
state.
When the data value is 1: The output state will be a low level.
These pins are set to input mode after a power on reset.
IO1
IO2
11
13
11
14
Output port
Output-only ports
The output state is determined by BO1 through BO4 in the serial
data.
When the data value is 0: The output state will be the open circuit
state.
When the data value is 1: The output state will be a low level.
A time base signal (8 Hz) is output from BO1 when TBC in the serial
data is set to 1.
BO1
BO2
BO3
BO4
7
8
9
10
7
8
9
10
Charge pump
output
PLL charge pump output
A high level is output when the frequency of the local oscillator signal
divided by N is higher than the reference frequency, and a low level
is output when that frequency is lower. This pin goes to the high-
impedance state when the frequencies match.
PD
18
19
Low-pass filter
amplifier
transistor
Connections for the MOS transistor used for the PLL active low-pass
filter.
AIN
AOUT
19
20
21
IF counter
The input frequency range is 0.4 to 15 MHz
The signal is passed directly to the IF counter.
The result is output, MSB first, through the DO pin.
Four measurement periods are supported: 4, 8, 32, and 64 ms.
IFIN
12
13
12
23
NC
—
NC pin
No connection
——
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC72121MA | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:CMOS IC PLL Frequency Synthesizers for Electronic Tuning |
| LC72121MA-AH | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LC72121MV | 制造商:未知厂家 制造商全称:未知厂家 功能描述: |
| LC72121V | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers for Electronic Tuning |
| LC72121V-D-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
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