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参数资料
| 型号： | LC72136NM |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 9/23页 |
| 文件大小： | 318K |
| 代理商： | LC72136NM |
No. 5608-17/23
LC72136N, 72136NM
IF Counter Operation
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.
The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the LC72136N
when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between the
point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF count at the end of the
measurement period must be read out during the period CTE is 1. This is because the IF counter is reset when CTE is set
to 0.
Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an IF
count operation. Auto-search techniques that use only the IF counter are not recommended, since it is possible for
IF buffer leakage output to cause incorrect stops at points where there is no station.
IFIN Minimum Sensitivity Ratings
f (MHz)
Note: Values in parentheses are actual performance values presented as reference data.
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock
determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.
IFS
0.4
≤ f < 0.5
0.5
≤ f < 8
8
≤ f ≤ 12
1: Normal mode
40 mVrms
(0.1 to 3 mVrms)
(1 to 10 mVrms)
0: Degradation mode
70 mVrms
(10 to 15 mVrms)
(30 to 40 mVrms)
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