参数资料
型号: LC72147V
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
封装: SSOP-24
文件页数: 4/22页
文件大小: 154K
代理商: LC72147V
No. 6675-12/22
LC72147V
Continued from preceding page.
No.
Control block/data
Content
Related data
Width selection for the phase error (E) detection function used to determine the PLL
locked/unlocked state. When a phase error greater than the E detection width from the
table occurs, the PLL circuit is seen as in the unlocked state. When unlocked, the
detection pin (DO or I/O-5) goes to the low state.
ULD
DT0, DT1
(10)
Unlock state detection data
UL0, UL1
Crystal oscillator selection data
*: After the power-on reset, 10.25 MHz is selected.
Crystal oscillator buffer (XBUF) output control data
XB = 0: Buffer output is turned off. (This mode is selected after the power-on reset.)
XB = 1: Buffer output is turned on.
R0 to R3
(11)
Crystal oscillator circuit
XS0, XS1
XB
Controls the phase comparator dead band.
*: The phase comparator operates in DZA mode after the power-on reset.
(12)
Phase comparator control data
DZ0, DZ1
Bit that forcible sets the charge pump output to the low level.
DLC = 1: Low level
DLC = 0: Normal operation
*: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping
the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to
escape from the deadlocked state. Normal operation is selected after the power-on reset.
(13)
Charge pump control data
DLC
IC test control data
These bits must be set as follows during normal operation.
TEST0 = 0
TEST1 = 0
TEST2 = 0
*: After the power-on reset, the test data is all set to zero.
(14)
IC test data
TEST0
TEST1
TEST2
UL1
UL0
E detection width
Detection pin output
0
Stopped
Open
0
1
0
E is output directly
1
0
±0.5 s
E is extended by 1 to 2 ms.
1
±1 s
E is extended by 1 to 2 ms.
1 to 2 ms
Unlocked state output
Extended
D0
I/O5
E
XS1
XS0
X’tal OSC
0
4.5 MHz
0
1
7.2 MHz
1
0
10.25 MHz
1
10.35 MHz
DZ1
DZ0
Dead band mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
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