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参数资料
| 型号： | LC7219 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24 |
| 封装： | SDIP-24 |
| 文件页数： | 11/12页 |
| 文件大小： | 212K |
| 代理商： | LC7219 |
LC7219, 7219M
No.3661–8/12
General-purpose Counter
The 20-bit general-purpose counter is used for both frequency and period measurement as shown in figure 8. The
measurement mode is selected by bits SC and SF as shown in table 7. The counter value is output on DO with the msb
first.
Figure 8. General-purpose counter
Table 7. General-purpose counter mode selection
C
SF
St
r
o
p
t
u
p
n
Ir
e
t
e
m
a
r
a
P
1
×
R
T
C
H)
e
v
a
w
e
n
i
s
(
t
n
e
m
e
r
u
s
a
e
m
y
c
n
e
u
q
e
r
F
01
R
T
C
L)
e
v
a
w
e
n
i
s
(
t
n
e
m
e
r
u
s
a
e
m
y
c
n
e
u
q
e
r
F
00
R
T
C
L)
e
v
a
w
e
s
l
u
p
(
t
n
e
m
e
r
u
s
a
e
m
d
o
i
r
e
P
Note
× = don’t care
In frequency measurement mode, the input cycles during a 30 or 60 ms interval are counted. Either LCTR or HCTR
can be selected as the counter input.
In period measurement mode, LCTR is the single input, and the 900kHz cycles in one or two periods of the LCTR
signal are counted.
The counter starts when the CTEN flag is set. The serial input data is latched in on the falling edge of CE. The input
data on HCTR or LCTR should be input within 10 ms of this transition.
The period or frequency measurement count should be read while CTEN is still set to 1, as the counter is reset by
setting CTEN to 0. CTEN should be set to 0 before each measurement.
The LCTR signal is passed directly to the counter input. The HCTR signal is passed through a divide-by-eight
prescaler. The actual HCTR frequency is, therefore, eight times the measured frequency.
When the universal counter is used as the IF counter, the state of the IF-IC SD (station detect) signal must be checked
by the microcontroller, and the IF counter buffer output turned on only after the SD signals are activated. Auto-search
techniques using only the IF counter are not advisable since it is possible that the search can stop incorrectly at a
location that does not have a station due to the IF counter buffer output leakage.
DO goes HIGH when the CTEN flag is set to 1, and LOW when frequency or period measurement is completed. DO
can be monitored to check for measurement completion. The timing for the general-purpose counter is shown in figure
9.
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相关代理商/技术参数 |
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|---|---|
| LC72191 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JMA-AH | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LC72191M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191M-TLM-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Tape and Reel |
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