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参数资料
| 型号： | LC7219M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 2/12页 |
| 文件大小： | 212K |
| 代理商： | LC7219M |
LC7219, 7219M
No.3661–10/12
Using DO to monitor for measurement completion
DO can be used to monitor for frequency or period measurement completion as shown in figure 11.
Notes
1. Setting CTEN to 1 sets DO HIGH and prevents IN0 from affecting DO.
2. DO goes LOW when the measurement is complete.
Figure 11. Measurement completion timing
Phase-locked Loop
Reading the PLL unlock flags
The PLL unlock flags are set on the rising edge of the internal ΦERROR signal and cleared on the rising edge of the CE
signal. In serial data output mode, the flags set since the last rising edge of CE can be read. This is the interval t0 to t1
shown in figure 12.
Each PLL unlock flag is set if the corresponding time interval is exceeded as follows.
UL0 is set when ΦERROR≥1.11s
UL1 is set when ΦERROR≥2.22s
UL2 is set when ΦERROR≥3.33s
UL3 is set when ΦERROR≥0.55s
The flag values for different error ranges, where ΦERROR is the phase error for the 7.2MHz crystal, are as follows.
If ΦERROR<0.55s, UL=0000
If 0.55s≤ΦERROR<1.11s, UL=1000
If 1.11s≤ΦERROR<2.22s, UL=1001
If 2.22s≤ΦERROR<3.33s, UL=1011
If 3.33s≤ΦERROR, UL=1111
Figure 12. PLL unlock flag timing
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