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参数资料
| 型号： | LC75010W |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | 14 X 14 MM, SQFP-100 |
| 文件页数： | 12/12页 |
| 文件大小： | 128K |
| 代理商： | LC75010W |
No. N7349-9/12
LC75010W
tCL
tEH
tES
tHD
tSU
Old
New
tLC
tDH
tDC
tEL
tCH
≈
When CL is stopped at the low level
VIL
VIH
VIH
VIL
DO
CL
DI
CE
≈
tCL
tEH
tES
tHD
tSU
Old
New
tLC
tDH
tDC
tEL
tCH
≈
When CL is stopped at the high level
VIL
VIH
VIL
VIH
DO
Internal
data latch
CL
DI
CE
≈
Internal
data latch
Serial Data Timing
CL: Normally high
CL: Normally low
Reset Timing
After power has been applied, and after crystal oscillator operation and PLL circuit operation have stabilized, a reset must
be applied at the point that the Vref voltages (Vref1, Vref2, and Vref3) exceed the minimum level of 2.35 V. The reset
period must be set up to include a period of at least 0.5 s during which the reset signal is held fixed at the low level.
Audio processing (audio input/audio output) cannot be performed during the A/D converter calibration period (100 ms),
which directly follows the reset.
Note on Changes to the DSP Core Main Clock
The LC75010W DSP core main clock can be switched by setting the TEST8 pin either low or high as shown below.
TEST8
DSP core main clock (Crystal oscillator: 16.9344 MHz)
Low (DVSS)
38.1024 MHz
High (DVDD 3.3)
40.2192 MHz
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