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参数资料
| 型号： | LC75010W |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | 14 X 14 MM, SQFP-100 |
| 文件页数： | 8/12页 |
| 文件大小： | 128K |
| 代理商： | LC75010W |
No. N7349-5/12
LC75010W
Pin Functions
Pin No.
Pin name
Input/Output (I/O)
Function
97
AINRP1
I
Analog BTL input (Rch +)
94
AINRN1
I
Analog BTL input (Rch -)
77
AINLP1
I
Analog BTL input (Lch +)
80
AINLN1
I
Analog BTL input (Lch -)
89
AINRP2
I
Analog OTL input1 (Rch +)
85
AINLP2
I
Analog OTL input1 (Lch +)
92
AINRP3
I
Analog OTL input2 (Rch +)
82
AINLP3
I
Analog OTL input2 (Lch +)
93
AINRP4
I
Analog OTL input3 (Rch +)
81
AINLP4
I
Analog OTL input3 (Lch +)
Standby mode (active low)
Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power
down mode").
34
PWDB
I
In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole
LC75010W goes to the stopped state. This pin must be held at the high level during normal
operation.
Reset (active low)
35
RSTB
I
A reset is normally applied at power on, after recovering from a temporary power outage, and after
returning from standby mode ("power down mode").
Interrupt (active low) (Software clip input (0/1))
40
INTB
I
Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier
output.
10
TEST0
I/O
Test pin
11
TEST1
I/O
Test pin
12
TEST2
I/O
Test pin
13
TEST3
I/O
Test pin
14
TEST4
I/O
Test pin
17
TEST5
I/O
Test pin
18
TEST6
I/O
Test pin
19
TEST7
I/O
Test pin
20
TEST8
I/O
Test pin
21
TEST9
I/O
Test pin
22
TEST10
I/O
Test pin
41
TEST11
I/O
Test pin
44
TEST12
I/O
Test pin
45
TEST13
I/O
Test pin
46
TEST14
I/O
Test pin
49
XIN
I
Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz)
50
XOUT
O
Crystal output
27
VCO
I
VCO control
28
PDO
O
Charge pump output
36
CE
I
CCB enable
37
CL
I
CCB clock
38
DI
I
Data in
39
DO
O
Data out
CCB ready monitor
33
BUSY
O
Outputs the state of the DSP CCB receive buffer.
A low-level output from the BUSY pin indicates that the buffer is empty.
A high-level output indicates that command data is present in the receive buffer.
74
VFLO
O
Volume front Lch output
73
VFLI
I
Volume front Lch input
71
VFRO
O
Volume front Rch output
70
VFRI
I
Volume front Rch input
58
VRLO
O
Volume rear Lch output
59
VRLI
I
Volume rear Lch input
55
VRRO
O
Volume rear Rch output
56
VRRI
I
Volume rear Rch input
Continued on next page.
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