LC7868/69 interface
This interface is identical to that described in item 2 above, except that the SBCK polarity is reversed, i.e., the shift
occurs on a rising edge.
3. DRAM Interface: Pins 1A0 to 1A7, 1DB0 to 1DB3, RAS, CAS, 1WE, OE, 2A0 to 2A7, 2DB0 to 2DB3, 2WE and
M1/M2
The LC7871E and LC7871NE use external 64k by 4-bit DRAMs.
Two external DRAMs are required for CD-EG. Only one external DRAM is required for CD-G. The M1/M2 pin
setting must match the number of DRAMs actually used. When single memory chip operation is selected by setting
the M1/M2 pin high, the pins 2DB0 to 3 function in output mode. Thus the pins 2A0 to 7, 2DB0 to 3, 2WE and 2OE
can be left open.
4. Display Format: Pins DEN, N/P1, N/P2, CSYNC, VRESET, HRESET, YS, VIDEO, PALID, TRANS and TRANS0
to TRANS5
Data which has undergone error detection and correction is encoded by the built-in RGB encoder, converted to
analog by the 8-bit D/A converter, and output from the VIDEO pin. This system can handle both PAL and NTSC
modes, and either mode can be specified from the N/P pin. See item 1 for the states of the pins in the PAL and
NTSC modes.
The YS, VRESET, HRESET, PALID, TRANS and TRANS0 to TRANS5 pins are used in superimposition
processing.
The DEN pin is a display control pin. When this pin is at a low level, the internal font data is output, and when at a
high level, the color data loaded into the registers is output. The default state is blue.
No. 4861-13/19
LC7871E, 7871NE