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参数资料
| 型号： | LC78836M |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 16-BIT DAC, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 9/12页 |
| 文件大小： | 310K |
| 代理商： | LC78836M |
Soft muting
Soft muting is implemented using the on-chip digital attenuator.
The attenuator attenuation is given by the following formula.
20 Log (ATT/64) dB
Here, ATT is an integer between 0 and 64 inclusive. However, the attenuation is –
∞ when ATT = 0. When the
MUTE pin is set high, the ATT value is reduced one level at a time towards zero, and the attenuation changes,
moving towards –
∞. When the MUTE pin is set low, the ATT value is increased one level at a time towards 64,
and the attenuation changes, moving towards 0 dB. The time required for the soft mute function to complete is
about 1024/fs.
Noise shaper
The LC78836M uses a first-order noise shaper to reduce re-quantization noise in the output of the DF calculations.
Double-speed support
The LC78836M supports double-speed CD playback when the D/N pin is set high. In this mode, the BCLK,
LRCK, and DATA inputs should be input with twice the frequencies they have in standard-speed mode. Note that
the system clock (the XIN pin clock) has the same frequency as it does in standard-speed mode. The LC78836M
supports double-speed operation when the system clock is a 384 fs or 512 fs clock, but does not support this mode
for 392 fs and 448 fs clocks. Since the LC78836M enters test mode for these settings, they should not be used.
Standard-speed mode: D/N pin = low
Double-speed mode: D/N pin = high
2. Initialization
The LC78836M must be initialized when power is first applied or when the system clock is switched. Initialization is
executed by setting the INITB pin low. While that pin is low, after the power supply voltage stabilizes, input the
XIN, BCLK, and LRCK signals, and wait at least one LRCK period, as shown in the figure below.
When INITB is low, all 16 bits of the digital filter outputs will be zeros, and the D/A converter outputs (CH1OUT
and CH2OUT) will be analog 0 (a potential essentially equal to (VREFH + VREFL)/2).
No. 5127-6/12
LC78836M
相关PDF资料 |
PDF描述 |
|---|---|
| LC7883K | SERIAL INPUT LOADING, 16-BIT DAC, PDIP28 |
| LC7883KM | SERIAL INPUT LOADING, 16-BIT DAC, PDSO28 |
| LC78850 | SERIAL INPUT LOADING, 18-BIT DAC, PDIP42 |
| LC78850Q | SERIAL INPUT LOADING, 18-BIT DAC, PQFP44 |
| LC78855KM | SERIAL INPUT LOADING, 1-BIT DAC, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC7883K | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC7883KM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:16-bit Digital Filter and Digital-to-analog Converters for Digital Audio |
| LC7883M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:LC7883M |
| LC78840M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Four-times or Eight-times Oversampling Digital Filter |
| LC78845Q | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Sample Rate Converter for Digital Audio |
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