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参数资料
| 型号： | LC83210W |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, SQFP-48 |
| 文件页数： | 11/11页 |
| 文件大小： | 471K |
| 代理商： | LC83210W |
LC83210W
No.7974-9/11
Table 4 External Configuration Mode 3 Operating Clock Configuration Register
PLL1
PLL0
PLL SW
Example1. 48kHz
Example2.
0
2 times
48kHz
×512fs×2 = 49.152MHz
27MHz
×2 = 54MHz
0
1
4 times
48kHz
×256fs×4 = 49.152MHz
13.5MHz
×4 = 54MHz
1
0
Reserve
Not use
1
Reserve
Not use
Note: The operating clock of the LC83210W has a frequency of approximately 50MHz. Due to this setting, an
operating clock with a frequency of approximately 50MHz is generated by doubling or quadrupling the clock
frequency, which has been input to the PLL circuit inside the IC chip.
Other Details
MUTE: This applies the muting function to the IC chip.
STEREO: This outputs the SDI0 input audio data to SDO using the bypass. The SDI1 data and SDI2 data are ignored.
When Bypass on is set for STEREO, the MUTE setting is canceled.
PLL STOP: This shuts down the PLL clock, and establishes power-saving mode to reduce power consumption. After
this setting has been released, resetting must be initiated for the IC, and the control registers must be set
again.
Stereo Mixdown: The calculation formulas below are employed for the stereo down-mix filter which is used in this
mode. (This mode is designed for Dolby Headphones.)
Lo = 0.5 (L+0.707C+LS+LFE)
Ro = 0.5 (R+0.707C+RS+LFE)
Table of DH&DVS processing correspondences by sampling frequency: The LC83210W has ROM coefficients that are
used for the processing of the places marked with “ ” in the table below.
Table 5
32kHz sample
44.1kHz sample
48kHz sample
96kHz sample
2ch
5.1ch
2ch
5.1ch
2ch
5.1ch
2ch
5.1ch
DH1
×
DH2
×
DH3
×
REFERENCE
×
WIDE
×
Mixdown
L/R Bypass
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