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| 型号： | LC83210W |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | 7 X 7 MM, SQFP-48 |
| 文件页数： | 8/11页 |
| 文件大小： | 471K |
| 代理商： | LC83210W |
LC83210W
No.7974-6/11
Block Diagram
Audio Input/Output Interfaces (LRCLOCK, SCLOCK, SDI0, SDI1, SDI2, SDO)
This interface is for the serial input of stereo or multi-channel audio signals that have been processed by CD-DA, MD,
MP3 or DVD decoders, and it performs Dolby headphone and virtual speaker processing for the input audio data. The
processed audio data is output to SDO, and connected to a DA converter or other chip.
L/R signals must be input to SDI0; Ls/Rs signals to SDI1; and C/LFE signals to SDI2. The LR clock (LRCLOCK) and
bit clock (SCLOCK) must be used for both input and output. (For details on the timing relating to the audio input/output
interface, refer to “Audio interface timing.”)
If the audio data format is 24 bits IIS (FM2 = 1, FM1 = 0, FM0 = 0) or 24 bits left-justified (FM2 = 1, FM1 = 0, FM0 =
1), “0” must be set for the low-order bits of the audio interface setting when the output from the decoder (such as the
AC-3 decoder) is under 24 bits.
When stereo signals are to be processed, “L” must be input to SDI1/SDI2.
ILC05569
FIR Filter
Core
(DSP)
Control register
Program
ROM
15kW
× 32bits
11.5k
× 24bits
In
p
u
tr
egi
st
er
LR Ls
Rs
C
LFE
D
a
ta
I/O
I/
F
PLL
RESET/STOP
PLL STOP
RESET
SYS CLK
LRCLOCK
SCLOCK
SDI0, 1, 2
SDO
RESET
P
LL
S
T
O
P
ENABLE
CLOCK
DATA
3
R
MCLOCK
VCNT
PDO
Data
RAM
O
u
tp
ut
r
egi
st
er
L
R
Host interface
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