参数资料
型号: LC8904Q
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封装: QFP-48
文件页数: 8/20页
文件大小: 321K
代理商: LC8904Q
The CLK, CLKMD, CLKOUT1, and CLKOUT2 Pins
The output clocks for the CLKOUT1 and CLKOUT2 clock output pins is selected by the CLK and CLKMD pins.
Note: 1. The crystal oscillator clock is output in analog source mode.
2. The 256fs clock has a H:L duty ratio of 2:1 when the CLK pin is low.
The SUB1 and SUB2 Pins
These pins indicate the sampling frequency of the input data.
The state “#1” is indicated on a PLL lock error and in analog source mode.
Also note that the DATAOUT and EMPHA pins will output low levels in this state.
The EMPHA Pin
The ERROR pin and Error Processing
ERROR pin: When an error exists in the input data or when the PLL circuit is in the unlocked state, this pin goes high
and holds that high level for about 200 to 300 ms after data demodulation returns to normal. The table below lists the
data processing applied when an error occurs.
Note: * The CRC flags go low when a PLL lock error occurs.
Note: PLL lock error determination is performed starting from preamble detection.
The XMODE Pin
This pin is used for system reset. The system will start to operate normally if this pin is set high after the power supply
has risen to at least 4.5 V. If XMODE is set low, the VCO free-running clock will be output from the CLKOUT1 pin.
After application of power, the system will be reset if the XMODE pin is set low again.
No. 5014-16/20
LC8904Q
CLK
CLKOUT*1
L
Outputs a 384fs clock
H
Outputs a 512fs clock
CLKMD
CLKOUT2
L
Outputs a 256fs clock*2
H
Outputs a 128fs clock
Pin
32 kHz
44.1 kHz
48 kHz
#1
SUB1
H
L
H
SUB2
H
L
H
L
Pin
Emphasis applied
Emphasis not applied
Analog source mode
EMPHA
H
L
Type of error
DATAOUT
SUB1, SUB2
C bit
Sub Q*
Up to eight consecutive parity errors
Previous data
Output
Eight or more consecutive parity errors
L
Output
PLL lock error
L
#1
L
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