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参数资料
| 型号： | LC99062-W50 |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 3/7页 |
| 文件大小： | 111K |
| 代理商： | LC99062-W50 |
Pin Functions
I/O
→ I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
No. 5073-3/7
LC99062-W50
Pin No.
Symbol
I/O
Function
1
TV
I
0: NTSC, 1: PAL
2
MIRROR
I
0: Normal, 1: Mirror
3
VDD
P
4
VSS
P
5
FSC4
I
CLK (from LC99052) NTSC: 14.31818 MHz, PAL: 14.1875 MHz
6
VD62
I
VD (from LC99052)
7
HD62
I
HD (from LC99052)
8
APTSW
I
Aperture switch
0: Off, 1: On
9
HTCLK
I
CLK = 8/3fsc (from LC99052)
10
TESDATA
I
0: Run
11
CDSIN0
I
8-bit data input (from LC99052) (LSB)
12
CDSIN1
I
8-bit data input (from LC99052)
13
CDSIN2
I
8-bit data input (from LC99052)
14
CDSIN3
I
8-bit data input (from LC99052)
15
CDSIN4
I
8-bit data input (from LC99052)
16
CDSIN5
I
8-bit data input (from LC99052)
17
CDSIN6
I
8-bit data input (from LC99052)
18
CDSIN7
I
8-bit data input (from LC99052) (MSB)
19
VDD
P
20
VSS
P
21
OT1
O
Output channel1 = CH1 (LSB)
22
OT2
O
Output channel1 = CH1
23
OT3
O
Output channel1 = CH1
24
OT4
O
Output channel1 = CH1
25
OT5
O
Output channel1 = CH1
26
OT6
O
Output channel1 = CH1
27
OT7
O
Output channel1 = CH1
28
OT8
O
Output channel1 = CH1 (MSB)
29
OT24
O
Output channel3 = CH3 (MSB)
30
OT23
O
Output channel3 = CH3
31
OT22
O
Output channel3 = CH3
32
OT21
O
Output channel3 = CH3
33
OT20
O
Output channel3 = CH3
34
OT19
O
Output channel3 = CH3
35
OT18
O
Output channel3 = CH3
36
OT17
O
Output channel3 = CH3 (LSB)
37
OT16
O
Output channel2 = CH2 (MSB)
38
OT15
O
Output channel2 = CH2
39
OT14
O
Output channel2 = CH2
40
VSS
P
41
VDD
P
42
OT13
O
Output channel2 = CH2
43
OT12
O
Output channel2 = CH2
44
OT11
O
Output channel2 = CH2
45
OT10
O
Output channel2 = CH2
46
OT9
O
Output channel2 = CH2 (LSB)
47
REGSEL0
I
(REGRES) 0: Register initialization 1: Register modification allowed
48
REGSEL1
I
(CLKS) Serial clock input
49
REGSEL2
I
(DATAS) Serial data input
50
REGSEL3
I
51
REGSEL4
I
REGSEL [4:0] = (11110) or (11**1); OT (24 to 1) → High impedance
52
CSSET1
I
Must be set according to the phase of the LC99052 A/D converter clock. (This is true for pin 81 as well.)
Recommended value for current conditions: 1
53
SUPER
I
Superimpose pulse input 1; superimpose 0; camera through
54
CKEYH
O
Chrominance key out H; chrominance key
The delay time is changed by the settings of pins 85 and 86. See pins 85 and 86.
Continued on next page.
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