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参数资料
| 型号： | LC99062-W50 |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 4/7页 |
| 文件大小： | 111K |
| 代理商： | LC99062-W50 |
Continued from preceding page.
I/O
→ I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
No. 5073-4/7
LC99062-W50
Pin No.
Symbol
I/O
Function
55
BIN8
I
8-bit data input (MSB)
56
BIN7
I
8-bit data input
57
BIN6
I
8-bit data input
58
BIN5
I
8-bit data input
59
BIN4
I
8-bit data input
60
BIN3
I
8-bit data input or register setting pin
61
BIN2
I
8-bit data input or register setting pin
62
BIN1
I
8-bit data input (LSB) or register setting pin
63
VDD
P
64
GIN8
I
8-bit data input (MSB)
65
GIN7
I
8-bit data input
66
GIN6
I
8-bit data input
67
GIN5
I
8-bit data input
68
GIN4
I
8-bit data input
69
GIN3
I
8-bit data input or register setting pin
70
GIN2
I
8-bit data input or register setting pin
71
GIN1
I
8-bit data input (LSB) or register setting pin
72
VSS
P
73
RIN8
I
8-bit data input (MSB)
74
RIN7
I
8-bit data input
75
RIN6
I
8-bit data input
76
RIN5
I
8-bit data input
77
RIN4
I
8-bit data input
78
RIN3
I
8-bit data input or register setting pin
79
RIN2
I
8-bit data input or register setting pin
80
RIN1
I
8-bit data input (LSB) or register setting pin
81
CSSET2
I
Must be set according to the phase of the LC99052 A/D converter clock. (This is true for pin 52 as well.)
Recommended value for current conditions: 1
Output mode select
000: Video (OT1 to OT8), ICON (OT24)
001: R (OT1 to OT8), G (OT9 to OT16), B (OT17 to OT24)
82
OMODE0
I
010: R-Y (OT1 to OT8), Y (OT9 to OT16), B-Y (OT17 to OT24)
83
OMODE1
I
011: Y (OT1 to OT8), C (OT9 to OT16), CSYNC (OT24)
84
OMODE2
I
100: Y (OT1 to OT8), U/V (OT9 to OT16), UVCONT (OT24)
101: VBS (OT1 to OT8), Y (OT12 to OT9), R-Y (OT16, OT15), B-Y (OT14, OT13)
110: VBS (OT1 to OT8), Y + CSYNC (OT9 to OT16), C (OT17 to OT24)
111: Y/U/V (OT1 to OT8)
Input mode select
00: R (RIN4 to RIN8), G (GIN4 to GIN8), B (BIN4 to BIN8)*1
85
IMODE0
I
01: R (RIN4 to RIN8), G (GIN4 to GIN8), B (BIN4 to BIN8)*2
86
IMODE1
I
10: R (RIN1 to RIN8), G (GIN1 to GIN8), B (BIN1 to BIN8)*1
11: Y (RIN1 to RIN8), V (GIN1 to GIN8), U (BIN1 to BIN8)*1
Note: 1. The output is synchronized with the chrominance key out.
2. The chrominance key out is output 16 clock cycles in advance of this output.
87
WBMD1
I
White balance mode SW1
88
WBHLH
I
Auto white balance hold; 1: Hold, 0: Auto
Note: * Hold this pin low when the internal register is used.
89
VDD
P
90
VSS
P
91
WBMD2
I
White balance mode SW2
92
WBMD3
I
White balance mode SW3
93
REG1
I
Register setting pin
94
REG2
I
Register setting pin
95
REG3
I
Register setting pin
96
REG4
I
Register setting pin
97
REG5
I
Register setting pin
98
REG6
I
Register setting pin
99
REG7
I
Register setting pin
100
REG8
I
Register setting pin
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