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参数资料
| 型号： | LCK4802 |
| 英文描述： | Low-Voltage PECL Differential Clock |
| 中文描述： | 低电压PECL差分时钟 |
| 文件页数： | 1/10页 |
| 文件大小： | 156K |
| 代理商： | LCK4802 |
Preliminary Data Sheet
July 2001
LCK4802
Low-Voltage PECL Differential Clock
General
The LCK4802 is a low-voltage, 3.3 V PECL
differential clock synthesizer. The LCK4802 supports
two differential PECL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multiple processor systems that
require PECL differential inputs. The LCK4802
contains a fully integrated PLL (phase-locked loop)
which multiplies the PECL_CLK input frequency to
match individual processor clock frequencies. The
PLL can be bypassed so that the PCLK outputs are
fed from the PECL_CLK or PECL_CLK input for test
purposes. All outputs are powered from a 2 V
external supply to reduce on-chip power
consumption. All outputs are PECL. The PLL can
operate in the internal feedback mode, or in the
external feedback mode for board level debugging
applications.
Features
s
Two fully selectable clock inputs.
s
Fully integrated PLL.
s
336 MHz to 1 GHz output frequencies.
s
PECL outputs.
s
PECL reference clock.
s
32-pin TQFP package.
Description
2274.b (F)
Figure 1. LCK4802 Logic Diagram
PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)
TESTM (PULL-UP)
PLLREF_EN (PULL-UP)
REF_SEL (PULL-UP)
PECL_CLK (PULL-UP)
EXTFB_IN (PECL)
(PULL-UP)
(PULL-DOWN)
EXTFB_EN (PULL-UP)
SEL[4:0] (PULL-UP)
RESET (PULL-UP)
PLL_BYPASS (PULL-UP)
EXTFB_OUT (PECL)
PCLK0
PCLK1
PLL
/N
/M
DECODE
0
1
0
1
0
1
PCLK0 (PECL)
PCLK1 (PECL)
EXTFB_OUT
PECL_CLK (PULL-UP)
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